On OpenVMS x86-64 systems, the compiler provides three sets of built-
ins:
o Alpha instruction built-ins that are used to generate x86-64
instructions for the corresponding Alpha instruction.
o Itanium instruction built-ins that are used to generate x86-64
instructions for the correspoinding Itanium instruction.
o x86-64 instruction built-ins that are used to generate the
specified instruction.
On OpenVMS x88-64 systems, all of the Alpha PALcode built-ins are
emulated by means of macros provided by the system.
The sets of built-ins are presented in tables. The second column
of each table specifies the operands the built-in expects, where:
WL = write longword
ML = modify longword
AL = address of longword
WQ = write quadword
RQ = read quadword
MQ = modify quadword
AQ = address of quadword
AB = address of byte
AW = address of word
WB = write byte
WW = write word
NOTE
Be careful when mixing built-ins with VAX MACRO instructions
on the same registers. The code generated by the compiler
expects registers to contain 32-bit sign-extended values,
but it is possible to create 64-bit register values that are
not in this format. Subsequent longword operations on these
registers could produce incorrect results.
Therefore, make sure to return registers to 32-bit sign-
extended format before using them in VAX MACRO instructions
as source operands. Note that loading the register with
a new value using a VAX MACRO instruction (such as MOVL)
returns it to this format.
Additional Information:
explode
extract