On OpenVMS x86-64 systems, the compiler provides three sets of built-
ins:
o Alpha instruction built-ins that are used to generate x86-64
instructions for the corresponding Alpha instruction.
o Itanium instruction built-ins that are used to generate x86-64
instructions for the correspoinding Itanium instruction.
o x86-64 instruction built-ins that are used to generate the
specified instruction.
On OpenVMS x88-64 systems, all of the Alpha PALcode built-ins are
emulated by means of macros provided by the system.
The sets of built-ins are presented in tables. The second column
of each table specifies the operands the built-in expects, where:
WL = write longword
ML = modify longword
AL = address of longword
WQ = write quadword
RQ = read quadword
MQ = modify quadword
AQ = address of quadword
AB = address of byte
AW = address of word
WB = write byte
WW = write word
NOTE
Be careful when mixing built-ins with VAX MACRO instructions
on the same registers. The code generated by the compiler
expects registers to contain 32-bit sign-extended values,
but it is possible to create 64-bit register values that are
not in this format. Subsequent longword operations on these
registers could produce incorrect results.
Therefore, make sure to return registers to 32-bit sign-
extended format before using them in VAX MACRO instructions
as source operands. Note that loading the register with
a new value using a VAX MACRO instruction (such as MOVL)
returns it to this format.
1 – Alpha Instruction Built-Ins
Ported VAX MACRO code sometimes requires access to Alpha
native instructions to deal directly with a 64-bit quantity
or to include an Alpha instruction that has no VAX equivalent.
The compiler provides built-ins to allow you access to these
instructions. On OpenVMS I64 systems, the compiler generates
equivalent Itanium instructions. On OpenVMS x86-64 systems,
the compiler generates equivalent x86-64 instructions.
The following byte and word built-ins are included in the MACRO
compiler:
o EVAX_LDBU
o EVAX_LDWU
o EVAX_STB
o EVAX_STW
o EVAX_SEXTB
o EVAX_SEXTW
You use these built-ins in the same way that you use native VAX
instructions, using any VAX operand mode. For example, EVAX_
ADDQ 8(R0),(SP)+,R1 is legal. The only exception is that the
first operand of any Alpha load/store built-in (EVAX_LD*, EVAX_
ST*) must be a register.
The following table summarizes the Alpha built-ins supported by
the compiler. The built-ins that are Alpha-only (cannot be used
to generate or access Itanium instructions) are noted in the
table.
Functional on
Built-in Operands Description OpenVMS I64 or x86-64
EVAX_SEXTB <RQ,WB> Sign-extend byte Yes
EVAX_SEXTW <RQ,WW> Sign-extend word Yes
EVAX_SEXTL <RQ,WL> Sign-extend longword Yes
EVAX_LDBU <WQ,AB> Load zero-extended Yes
byte from memory
EVAX_LDWU <WQ,AQ> Load zero-extended Yes
word from memory
EVAX_LDLL <WL,AL> Load longword locked Yes
EVAX_LDAQ <WQ,AQ> Load address of Yes
quadword
EVAX_LDQ <WQ,AQ> Load quadword Yes
EVAX_LDQL <WQ,AQ> Load quadword locked Yes
EVAX_LDQU <WQ,AQ> Load unaligned Yes
quadword
EVAX_STB <RQ,AB> Store byte from Yes
register to memory
EVAX_STW <RQ,AW> Store word from Yes
register to memory
EVAX_STLC <ML,AL> Store longword Yes
conditional
EVAX_STQ <RQ,AQ> Store quadword Yes
EVAX_STQC <MQ,AQ> Store quadword Yes
conditional
EVAX_STQU <RQ,AQ> Store unaligned Yes
quadword
EVAX_ADDQ <RQ,RQ,WQ> Quadword add Yes
EVAX_SUBQ <RQ,RQ,WQ> Quadword subtract Yes
EVAX_MULQ <RQ,RQ,WQ> Quadword multiply Yes
EVAX_UMULH <RQ,RQ,WQ> Unsigned quadword Yes
multiply high
EVAX_AND <RQ,RQ,WQ> Logical product Yes
EVAX_OR <RQ,RQ,WQ> Logical sum Yes
EVAX_XOR <RQ,RQ,WQ> Logical difference Yes
EVAX_BIC <RQ,RQ,WQ> Bit clear Yes
EVAX_ORNOT <RQ,RQ,WQ> Logical sum with Yes
complement
EVAX_EQV <RQ,RQ,WQ> Logical equivalence Yes
EVAX_SLL <RQ,RQ,WQ> Shift left logical Yes
EVAX_SRL <RQ,RQ,WQ> Shift right logical Yes
EVAX_SRA <RQ,RQ,WQ> Shift right Yes
arithmetic
EVAX_EXTBL <RQ,RQ,WQ> Extract byte low Yes
EVAX_EXTWL <RQ,RQ,WQ> Extract word low Yes
EVAX_EXTLL <RQ,RQ,WQ> Extract longword low Yes
EVAX_EXTQL <RQ,RQ,WQ> Extract quadword low Yes
EVAX_EXTBH <RQ,RQ,WQ> Extract byte high Yes
EVAX_EXTWH <RQ,RQ,WQ> Extract word high Yes
EVAX_EXTLH <RQ,RQ,WQ> Extract longword high Yes
EVAX_EXTQH <RQ,RQ,WQ> Extract quadword high Yes
EVAX_INSBL <RQ,RQ,WQ> Insert byte low Yes
EVAX_INSWL <RQ,RQ,WQ> Insert word low Yes
EVAX_INSLL <RQ,RQ,WQ> Insert longword low Yes
EVAX_INSQL <RQ,RQ,WQ> Insert quadword low Yes
EVAX_INSBH <RQ,RQ,WQ> Insert byte high Yes
EVAX_INSWH <RQ,RQ,WQ> Insert word high Yes
EVAX_INSLH <RQ,RQ,WQ> Insert longword high Yes
EVAX_INSQH <RQ,RQ,WQ> Insert quadword high Yes
EVAX_TRAPB <> Trap barrier No
EVAX_MB <> Memory barrier Yes
EVAX_RPCC <WQ> Read process cycle No
counter
EVAX_CMPEQ <RQ,RQ,WQ> Integer signed Yes
compare, equal
EVAX_CMPLT <RQ,RQ,WQ> Integer signed Yes
compare, less than
EVAX_CMPLE <RQ,RQ,WQ> Integer signed Yes
compare, less equal
EVAX_CMPULT <RQ,RQ,WQ> Integer unsigned Yes
compare, less than
EVAX_CMPULE <RQ,RQ,WQ> Integer unsigned Yes
compare, less equal
EVAX_BEQ <RQ,AQ> Branch equal Yes
EVAX_BLT <RQ,AQ> Branch less than Yes
EVAX_BNE <RQ,AQ> Branch not equal Yes
EVAX_CMOVEQ <RQ,RQ,WQ> Conditional Yes
move/equal
EVAX_CMOVNE <RQ,RQ,WQ> Conditional move/not Yes
equal
EVAX_CMOVLT <RQ,RQ,WQ> Conditional move/less Yes
than
EVAX_CMOVLE <RQ,RQ,WQ> Conditional move/less Yes
or equal
EVAX_CMOVGT <RQ,RQ,WQ> Conditional Yes
move/greater than
EVAX_CMOVGE <RQ,RQ,WQ> Conditional Yes
move/greater or equal
EVAX_CMOVLBC <RQ,RQ,WQ> Conditional move/low Yes
bit clear
EVAX_CMOVLBS <RQ,RQ,WQ> Conditional move/low Yes
bit set
EVAX_MF_FPCR <WQ> Move from floating- No
point control
register
EVAX_MT_FPCR <WQ,RQ> Move to floating- No
point control
register
EVAX_ZAP <RQ,RQ,WQ> Zero bytes Yes
EVAX_ZAPNOT <RQ,RQ,WQ> Zero bytes with NOT Yes
mask
2 – Itanium[R] Instruction Built-Ins
Built-in Operands Description
IA64_BREAK <RQ> Generate a break instruction fault with
the immediate operand provided
IA64_ <WQ,RQ,RQ> Generate a move-from-indirect-register
GETINDREG instruction with the first operand as
the destination, the second operand
as a literal specifying which indirect
register file to access, and the third
operand as the index into the register
file
IA64_GETREG <WQ,RQ> Generate a move-from-application-
register or move-from-control-register
instruction with the first operand
as the destination and the second
operand as a literal specifying which
application or control register to read
IA64_LFETCH <RQ,RQ> Generate a line prefetch (LFETCH) or
IA64_LFETCH_EXCL <RQ,RQ> exclusive line prefetch (LFETCH.EXCL)
instruction using the first operand as
the address to prefetch and the second
operand for either the reg-base-update-
form or the imm-base-update-form. If
the operand is the literal zero, the
no-base-update-form will be used
IA64_PROBER <WQ,RQ,RQ> Generate a probe.r instruction with the
first argument as the destination, the
second argument as the virtual address
to probe, and the third operand as the
privilege level
IA64_PROBEW <WQ,RQ,RQ> Generate a probe.w instruction with the
first argument as the destination, the
second argument as the virtual address
to probe, and the third operand as the
privilege level
IA64_RSM <RQ> Generate a reset system mask ('RSM')
instruction with the specified mask
IA64_RUM <RQ> Generate a reset user mask ('RUM')
instruction with the specified mask
IA64_SETREG <RQ,RQ> Generate a move-to-application-register
or move-to-control-register instruction
with the first operand as a literal
specifying which application or control
register to write and the second
operand as the value to write into
the register
IA64_SRLZD <> Generate a serialize data ('SRLZD')
instruction
IA64_SRLZI <> Generate a serialize instruction
('SRLZI') instruction
IA64_SSM <RQ> Generate a set system mask ('SSM')
instruction with the specified mask
IA64_SUM <RQ> Generate a set user mask ('SUM')
instruction with the specified mask
IA64_TAK <WK,RQ> Generate a read translation access key
('TAK') instruction