invo_handle OpenVMS usage: invo_handle type: quadword access: read mechanism: by reference Handle for the invocation to be updated. invo_context OpenVMS usage: invo_context_blk type: structure access: read mechanism: by reference Address of a valid invocation context block that contains new register contents. At least one of the following register masks must be specified and contain a non-zero value. Each register that is set in the xx_mask argument is updated using the value found in the corresponding ICB field. For example, bit n set in gr_mask corresponds to IREG[n]. gr_mask OpenVMS usage: mask_word type: 16-bit vector access: read mechanism: by reference Address of a 16-bit bit vector, where each bit corresponds to a register field in the invo_context argument. Bits 0 through 15 correspond to IREG[0] through IREG[15]. Bit 0 corresponds to the argument information register (AI). If bit 7, which corresponds to SP, is set, then no changes are made. xmm_mask OpenVMS usage: mask_word type: 16-bit vector access: read mechanism: by reference Address of a 16-bit bit vector, where each bit corresponds to an SSE XMM register field in the XSAVE area, pointed to from the passed invo_context. Bit 7 corresponds to XMM7. ymm_mask OpenVMS usage: mask_word type: 16-bit vector access: read mechanism: by reference Address of a 16-bit bit vector, where each bit corresponds to an SSE YMM register field in the XSAVE area, pointed to from the passed invo_context. Bit 14 corresponds to YMM14. zmm_mask OpenVMS usage: mask_longword type: 32-bit vector access: read mechanism: by reference Address of a 32-bit bit vector, where each bit corresponds to an SSE ZMM register field in the XSAVE area, pointed to from the passed invo_context. Bit 21 corresponds to ZMM21. Note that if the same bit position is set in more than one of the xmm_mask, ymm_mask, and zmm_mask, the result is undefined. apr_mask OpenVMS usage: mask_longword type: 32-bit vector access: read mechanism: by reference Address of a 32-bit bit vector, where each bit corresponds to a register field in the pointed to Alpha pseudo-register area passed. Bits 0 through 31 correspond to Alpha registers R0 through R31. If bit 30, which corresponds to SP, or 31, which corresponds to RZ are set, then no changes are made. apr_mask OpenVMS usage: mask_quadword type: 64-bit vector access: read mechanism: by reference Address of a 64-bit bit vector, where each bit corresponds to a register field in the passed invo_context as follows: Bit 0=IP Bit 1=RFLAGS register Bit 2=FS register Bit 3=GS register Bit 4=MXCSR register Bit 5=FCW register Bit 6=FSW register Bits 7b63 are reserved Note that IP can only be updated when the invocaton in question has been interrupted (either by exception or by an interrupt) and is logically previous to an invocation with the OSSD$V_EXCEPTION_FRAME bit set. Note that MXCSR, FCW, and FSW can only be updated when there is a valid address and an XSAVE area in the invo_context.