/***************************************************************************/ /** **/ /** HPE CONFIDENTIAL. This software is confidential proprietary software **/ /** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/ /** authorized to be used, duplicated OR disclosed to anyone without the **/ /** prior written permission of HPE. **/ /** © 2023 Copyright Hewlett-Packard Enterprise Development, LP **/ /** **/ /** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/ /** proprietary software licensed by VMS Software, Inc., and is not **/ /** authorized to be used, duplicated or disclosed to anyone without **/ /** the prior written permission of VMS Software, Inc. **/ /** © 2023 Copyright VMS Software, Inc. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 9-Nov-2023 12:06:57 by OpenVMS SDL V3.7 */ /* Source: 26-AUG-2019 04:31:01 $1$DGA8345:[LIB_H.SRC]X86MSRDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $X86MSRDEF ***/ #ifndef __X86MSRDEF_LOADED #define __X86MSRDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* MSR register numbers */ #define X86_MSR$_IA32_APIC_BASE 27 #define X86_MSR$_IA32_ARCH_CAPABILITIES 266 #define X86_MSR$_IA32_EFER 3221225600 #define X86_MSR$_IA32_FMASK 3221225604 #define X86_MSR$_IA32_FS_BASE 3221225728 #define X86_MSR$_IA32_GS_BASE 3221225729 #define X86_MSR$_IA32_KERNEL_GS_BASE 3221225730 #define X86_MSR$_IA32_LSTAR 3221225602 #define X86_MSR$_IA32_MISC_ENABLE 416 #define X86_MSR$_PLATFORM_INFO 206 /* Contents are platform specific */ #define X86_MSR$_IA32_MTRRCAP 254 #define X86_MSR$_IA32_MTRR_DEF_TYPE 767 #define X86_MSR$_IA32_MTRR_FIX16K_80000 600 #define X86_MSR$_IA32_MTRR_FIX16K_A0000 601 #define X86_MSR$_IA32_MTRR_FIX4K_C0000 616 #define X86_MSR$_IA32_MTRR_FIX4K_C8000 617 #define X86_MSR$_IA32_MTRR_FIX4K_D0000 618 #define X86_MSR$_IA32_MTRR_FIX4K_D8000 619 #define X86_MSR$_IA32_MTRR_FIX4K_E0000 620 #define X86_MSR$_IA32_MTRR_FIX4K_E8000 621 #define X86_MSR$_IA32_MTRR_FIX4K_F0000 622 #define X86_MSR$_IA32_MTRR_FIX4K_F8000 623 #define X86_MSR$_IA32_MTRR_FIX64K_00000 592 #define X86_MSR$_IA32_MTRR_PHYSBASE0 512 #define X86_MSR$_IA32_MTRR_PHYSMASK0 513 #define X86_MSR$_IA32_MTRR_PHYSBASE1 514 #define X86_MSR$_IA32_MTRR_PHYSMASK1 515 #define X86_MSR$_IA32_MTRR_PHYSBASE2 516 #define X86_MSR$_IA32_MTRR_PHYSMASK2 517 #define X86_MSR$_IA32_MTRR_PHYSBASE3 518 #define X86_MSR$_IA32_MTRR_PHYSMASK3 519 #define X86_MSR$_IA32_MTRR_PHYSBASE4 520 #define X86_MSR$_IA32_MTRR_PHYSMASK4 521 #define X86_MSR$_IA32_MTRR_PHYSBASE5 522 #define X86_MSR$_IA32_MTRR_PHYSMASK5 523 #define X86_MSR$_IA32_MTRR_PHYSBASE6 524 #define X86_MSR$_IA32_MTRR_PHYSMASK6 525 #define X86_MSR$_IA32_MTRR_PHYSBASE7 526 #define X86_MSR$_IA32_MTRR_PHYSMASK7 527 #define X86_MSR$_IA32_MTRR_PHYSBASE8 528 #define X86_MSR$_IA32_MTRR_PHYSMASK8 529 #define X86_MSR$_IA32_MTRR_PHYSBASE9 530 #define X86_MSR$_IA32_MTRR_PHYSMASK9 531 #define X86_MSR$_IA32_PAT 631 #define X86_MSR$_IA32_STAR 3221225601 /* Machinecheck MSRs */ #define X86_MSR$_IA32_MCG_CAP 377 #define X86_MSR$_IA32_MCG_STATUS 378 #define X86_MSR$_IA32_MCG_CTL 379 #define X86_MSR$_IA32_MC0_CTL 1024 /* IA32_MC1_CTL at 404, etc... */ #define X86_MSR$_IA32_MC0_STATUS 1025 /* IA32_MC1_CTL at 405, etc... */ #define X86_MSR$_IA32_MC0_ADDR 1026 /* IA32_MC1_CTL at 406, etc... */ #define X86_MSR$_IA32_MC0_MISC 1027 /* IA32_MC1_CTL at 407, etc... */ #define X86_MSR$_IA32_MC0_CTL2 640 /* IA32_MC1_CTL2 at 281, etc... */ /* x2APIC MSRs */ #define X86_MSR$_IA32_X2APIC_APICID 2050 #define X86_MSR$_IA32_X2APIC_VERSION 2051 #define X86_MSR$_IA32_X2APIC_TPR 2056 /* Task priority */ #define X86_MSR$_IA32_X2APIC_PPR 2058 /* Processor priority */ #define X86_MSR$_IA32_X2APIC_EOI 2059 /* End of interrupt */ #define X86_MSR$_IA32_X2APIC_LDR 2061 /* Logical destination */ #define X86_MSR$_IA32_X2APIC_SPURIOUS_INT 2063 /* Spurious interrupt */ #define X86_MSR$_IA32_X2APIC_ISR_31_0 2064 /* In-service 31:0 */ #define X86_MSR$_IA32_X2APIC_ISR_63_32 2065 /* In-service 64:32 */ #define X86_MSR$_IA32_X2APIC_ISR_95_64 2066 /* In-service 95:64 */ #define X86_MSR$_IA32_X2APIC_ISR_127_96 2067 /* In-service 127:96 */ #define X86_MSR$_IA32_X2APIC_ISR_159_128 2068 /* In-service 159:128 */ #define X86_MSR$_IA32_X2APIC_ISR_191_160 2069 /* In-service 191:160 */ #define X86_MSR$_IA32_X2APIC_ISR_223_192 2070 /* In-service 223:192 */ #define X86_MSR$_IA32_X2APIC_ISR_255_224 2071 /* In-service 255:224 */ #define X86_MSR$_IA32_X2APIC_TMR_31_0 2072 /* Trigger mode 31:0 */ #define X86_MSR$_IA32_X2APIC_TMR_63_32 2073 /* Trigger mode 64:32 */ #define X86_MSR$_IA32_X2APIC_TMR_95_64 2074 /* Trigger mode 95:64 */ #define X86_MSR$_IA32_X2APIC_TMR_127_96 2075 /* Trigger mode 127:96 */ #define X86_MSR$_IA32_X2APIC_TMR_159_128 2076 /* Trigger mode 159:128 */ #define X86_MSR$_IA32_X2APIC_TMR_191_160 2077 /* Trigger mode 191:160 */ #define X86_MSR$_IA32_X2APIC_TMR_223_192 2078 /* Trigger mode 223:192 */ #define X86_MSR$_IA32_X2APIC_TMR_255_224 2079 /* Trigger mode 255:224 */ #define X86_MSR$_IA32_X2APIC_IRR_31_0 2080 /* Interrupt request 31:0 */ #define X86_MSR$_IA32_X2APIC_IRR_63_32 2081 /* Interrupt request 64:32 */ #define X86_MSR$_IA32_X2APIC_IRR_95_64 2082 /* Interrupt request 95:64 */ #define X86_MSR$_IA32_X2APIC_IRR_127_96 2083 /* Interrupt request 127:96 */ #define X86_MSR$_IA32_X2APIC_IRR_159_128 2084 /* Interrupt request 159:128 */ #define X86_MSR$_IA32_X2APIC_IRR_191_160 2085 /* Interrupt request 191:160 */ #define X86_MSR$_IA32_X2APIC_IRR_223_192 2086 /* Interrupt request 223:192 */ #define X86_MSR$_IA32_X2APIC_IRR_255_224 2087 /* Interrupt request 255:224 */ #define X86_MSR$_IA32_X2APIC_ERROR_STATUS 2088 /* Error status */ #define X86_MSR$_IA32_X2APIC_ICR 2096 /* Interrupt command */ #define X86_MSR$_IA32_X2APIC_LVT_TIMER 2098 /* LVT timer */ #define X86_MSR$_IA32_X2APIC_LVT_THERMAL 2099 /* LVT thermal sensor */ #define X86_MSR$_IA32_X2APIC_LVT_PERFMON 2100 /* LVT performance monitoring */ #define X86_MSR$_IA32_X2APIC_LVT_LINT0 2101 /* LVT LINT0 */ #define X86_MSR$_IA32_X2APIC_LVT_LINT1 2102 /* LVT LINT1 */ #define X86_MSR$_IA32_X2APIC_LVT_ERROR 2103 /* LVT Error */ #define X86_MSR$_IA32_X2APIC_LVT_INIT_COUN 2104 /* Initial timer count */ #define X86_MSR$_IA32_X2APIC_LVT_CUR_COUNT 2105 /* Current timer count */ #define X86_MSR$_IA32_X2APIC_LVT_DIV_CFG 2110 /* Divide configuration for timer */ #define X86_MSR$_IA32_X2APIC_LVT_SELF_IPI 2111 /* Self IPI */ /* Selected register offsets in xAPIC mode. */ #define X86_XAPIC$_APICID 32 #define X86_XAPIC$_VERSION 48 #define X86_XAPIC$_TASK_PRIORITY 128 #define X86_XAPIC$_EOI 176 #define X86_XAPIC$_ICR_LO 768 #define X86_XAPIC$_ICR_HI 784 #define X86_XAPIC$_LVT_TIMER 800 /* Machine-Specific Registers: */ /* In the register defintions, different fields can have different */ /* accessibility attributes. */ /* R/W field can be both read and written */ /* RO field can be read but not written */ /* R/WC0 field can be read, writing a zero to it clears the field */ #define EFER$M_SCE 0x1 #define EFER$M_RES1_7 0xFE #define EFER$M_LME 0x100 #define EFER$M_RES9 0x200 #define EFER$M_LMA 0x400 #define EFER$M_NXE 0x800 #define EFER$M_RES12_63 0xFFFFFFFFFFFFF000 typedef struct _ia32_efer { __union { unsigned __int64 efer$q_quadword; /* Entire quad register */ __struct { unsigned efer$v_sce : 1; /* SYSCALL Enable (R/W) [0] */ unsigned efer$v_res1_7 : 7; /* Reserved [1-7] */ unsigned efer$v_lme : 1; /* IA-32e Mode Enable (R/W) [8] */ unsigned efer$v_res9 : 1; /* Reserved [9] */ unsigned efer$v_lma : 1; /* IA-32e Mode Active (R) [10] */ unsigned efer$v_nxe : 1; /* Execute Disable Bit Enable (R/W) [11] */ unsigned efer$v_res12_63_1 : 32; unsigned efer$v_res12_63_2 : 20; /* Reserved [12-63] */ } efer$r_efer_bits; } efer$r_ia32_efer_ovrlay; } IA32_EFER; #if !defined(__VAXC) #define efer$q_quadword efer$r_ia32_efer_ovrlay.efer$q_quadword #define efer$v_sce efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_sce #define efer$v_lme efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_lme #define efer$v_res9 efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_res9 #define efer$v_lma efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_lma #define efer$v_nxe efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_nxe #endif /* #if !defined(__VAXC) */ #define MTRRCAP$M_FIXED_SUPPORTED 0x100 #define MTRRCAP$M_RES9 0x200 #define MTRRCAP$M_WC 0x400 #define MTRRCAP$M_SMRR 0x800 #define MTRRCAP$M_RES12_63 0xFFFFFFFFFFFFF000 typedef struct _ia32_mtrrcap { __union { unsigned __int64 mtrrcap$q_quadword; /* The entire quadword */ __struct { unsigned char mtrrcap$b_vcnt; /* Number of variable MTRRs [0-7] */ unsigned mtrrcap$v_fixed_supported : 1; /* Fixed MTRRs are supported [8] */ unsigned mtrrcap$v_res9 : 1; /* Reserved bit [9] */ unsigned mtrrcap$v_wc : 1; /* WC memory type supported [10] */ unsigned mtrrcap$v_smrr : 1; /* SMRR MTRRs supported [11] */ #if defined(__VAXC) unsigned mtrrcap$v_res12_63_1 : 32; unsigned mtrrcap$v_res12_63_2 : 20; #else unsigned __int64 mtrrcap$v_res12_63 : 52; /* Reserved bits [12-63] */ #endif } mtrrcap$r_cap_bits; } mtrrcap$r_mtrrcap_overlay; } IA32_MTRRCAP; #if !defined(__VAXC) #define mtrrcap$q_quadword mtrrcap$r_mtrrcap_overlay.mtrrcap$q_quadword #define mtrrcap$b_vcnt mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$b_vcnt #define mtrrcap$v_fixed_supported mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_fixed_supported #define mtrrcap$v_res9 mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_res9 #define mtrrcap$v_wc mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_wc #define mtrrcap$v_smrr mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_smrr #define mtrrcap$v_res12_63 mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_res12_63 #endif /* #if !defined(__VAXC) */ /* Memory type codes, as specified in IA32_PAT or the MTRRs */ #define IA32_MEMORY_TYPE$C_UC 0 /* Strong Uncacheable */ #define IA32_MEMORY_TYPE$C_WC 1 /* Write Combining */ #define IA32_MEMORY_TYPE$C_RES2 2 /* Reserved */ #define IA32_MEMORY_TYPE$C_RES3 3 /* Reserved */ #define IA32_MEMORY_TYPE$C_WT 4 /* Write Through */ #define IA32_MEMORY_TYPE$C_WP 5 /* Write Protected */ #define IA32_MEMORY_TYPE$C_WB 6 /* Write Back */ #define IA32_MEMORY_TYPE$C_UCMINUS 7 /* Uncached */ /* This type can only be encoded */ /* in IA32_PAT, not the MTRRs */ /* types 8 through 255 are reserved as well */ typedef struct _ia32_fixed_mtrr { __union { unsigned __int64 mtrr_fixed$q_quadword; /* The entire quadword */ unsigned char mtrr_fixed$b_fixed_type [8]; /* 8 type fields packed into the register */ } mtrr_fixed$r_mtrr_fixed_overlay; } IA32_FIXED_MTRR; #if !defined(__VAXC) #define mtrr_fixed$q_quadword mtrr_fixed$r_mtrr_fixed_overlay.mtrr_fixed$q_quadword #define mtrr_fixed$b_fixed_type mtrr_fixed$r_mtrr_fixed_overlay.mtrr_fixed$b_fixed_type #endif /* #if !defined(__VAXC) */ /* A variable MTRR range applies to a PFN if: */ /* (1) the valid bit is set for the pair in the PHYSMASK register, and */ /* (2) the PFN is greater than or equal to PHYSBASE */ /* (3) (PFN .and. PHYSMASK) = (PHYSBASE .and. PHYSMASK) */ /* */ /* Note that there are various rules to handle cases where mulitple variable */ /* ranges apply and/or where both a variable range and a fixed range apply. */ /* See the x86 architecture for details. */ #define MTRR_PHYSBASE$M_RES8_11 0xF00 #define MTRR_PHYSBASE$M_PHYSBASE 0xFFFFFFFFFF000 #define MTRR_PHYSBASE$M_RES52_63 0xFFF0000000000000 typedef struct _ia32_mtrr_physbase { __union { unsigned __int64 mtrr_physbase$q_quadword; /* The entire quadword */ __struct { unsigned char mtrr_physbase$b_type; /* Memory type for this range [0-7] */ unsigned mtrr_physbase$v_res8_11 : 4; /* Reserved bits [8-11] */ #if defined(__VAXC) unsigned mtrr_physbase$v_physbase_1 : 32; unsigned mtrr_physbase$v_physbase_2 : 8; #else unsigned __int64 mtrr_physbase$v_physbase : 40; /* Base PFN [12-51] */ #endif unsigned mtrr_physbase$v_res52_63 : 12; /* Reserved bits [52-63] */ } mtrr_physbase$r_physbase_bits; } mtrr_physbase$r_mtrr_physbase_over; } IA32_MTRR_PHYSBASE; #if !defined(__VAXC) #define mtrr_physbase$q_quadword mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$q_quadword #define mtrr_physbase$b_type mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$r_physbase_bits.mtrr_physbase$b_type #define mtrr_physbase$v_res8_11 mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$r_physbase_bits.mtrr_physbase$v_res8_11 #define mtrr_physbase$v_physbase mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$r_physbase_bits.mtrr_physbase$v_physbase #define mtrr_physbase$v_res52_63 mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$r_physbase_bits.mtrr_physbase$v_res52_63 #endif /* #if !defined(__VAXC) */ #define MTRR_PHYSMASK$M_RES0_10 0x7FF #define MTRR_PHYSMASK$M_VALID 0x800 #define MTRR_PHYSMASK$M_PHYSMASK 0xFFFFFFFFFF000 #define MTRR_PHYSMASK$M_RES52_63 0xFFF0000000000000 typedef struct _ia32_mtrr_physmask { __union { unsigned __int64 mtrr_physmask$q_quadword; /* The entire quadword */ __struct { unsigned mtrr_physmask$v_res0_10 : 11; /* Reserved bits [0-10] */ unsigned mtrr_physmask$v_valid : 1; /* Enables this variable range [11] */ #if defined(__VAXC) unsigned mtrr_physmask$v_physmask_1 : 32; unsigned mtrr_physmask$v_physmask_2 : 8; #else unsigned __int64 mtrr_physmask$v_physmask : 40; /* PFN range mask [12-51] */ #endif unsigned mtrr_physmask$v_res52_63 : 12; /* Reserved bits [52-63] */ } mtrr_physmask$r_physmask_bits; } mtrr_physmask$r_mtrr_physmask_over; } IA32_MTRR_PHYSMASK; #if !defined(__VAXC) #define mtrr_physmask$q_quadword mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$q_quadword #define mtrr_physmask$v_res0_10 mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$r_physmask_bits.mtrr_physmask$v_res0_10 #define mtrr_physmask$v_valid mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$r_physmask_bits.mtrr_physmask$v_valid #define mtrr_physmask$v_physmask mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$r_physmask_bits.mtrr_physmask$v_physmask #define mtrr_physmask$v_res52_63 mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$r_physmask_bits.mtrr_physmask$v_res52_63 #endif /* #if !defined(__VAXC) */ #define MTRR_DEF_TYPE$M_RES8_9 0x300 #define MTRR_DEF_TYPE$M_FIXED_MTRRS_ENABLE 0x400 #define MTRR_DEF_TYPE$M_MTRR_ENABLE 0x800 #define MTRR_DEF_TYPE$M_RES12_63 0xFFFFFFFFFFFFF000 typedef struct _ia32_mtrr_def_type { __union { unsigned __int64 mtrr_def_type$q_quadword; /* The entire quadword */ __struct { unsigned char mtrr_def_type$b_dflt_memory_type; /* Memory type if no other MTRR [0-7] */ /* pertains */ unsigned mtrr_def_type$v_res8_9 : 2; /* Reserved bits [8-9] */ unsigned mtrr_def_type$v_fixed_mtrrs_enable : 1; /* Enable bit for fixed-range MTRRs [10] */ unsigned mtrr_def_type$v_mtrr_enable : 1; /* Enable bit for all MTRRs [11] */ #if defined(__VAXC) unsigned mtrr_def_type$v_res12_63_1 : 32; unsigned mtrr_def_type$v_res12_63_2 : 20; #else unsigned __int64 mtrr_def_type$v_res12_63 : 52; /* Reserved bits [12-63] */ #endif } mtrr_def_type$r_deftype_bits; } mtrr_def_type$r_mtrr_deftype_overl; } IA32_MTRR_DEF_TYPE; #if !defined(__VAXC) #define mtrr_def_type$q_quadword mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$q_quadword #define mtrr_def_type$b_dflt_memory_type mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$b_dflt_memor\ y_type #define mtrr_def_type$v_res8_9 mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$v_res8_9 #define mtrr_def_type$v_fixed_mtrrs_enable mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$v_fixed_mt\ rrs_enable #define mtrr_def_type$v_mtrr_enable mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$v_mtrr_enable #define mtrr_def_type$v_res12_63 mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$v_res12_63 #endif /* #if !defined(__VAXC) */ typedef struct _ia32_pat { __union { unsigned __int64 ia32_pat$q_quadword; /* The entire quadword */ unsigned char ia32_pat$b_pa [8]; /* Page attribute */ /* High 5 bits are reserved and MBZ */ } ia32_pat$r_ia32_pat_overlay; } IA32_PAT; #if !defined(__VAXC) #define ia32_pat$q_quadword ia32_pat$r_ia32_pat_overlay.ia32_pat$q_quadword #define ia32_pat$b_pa ia32_pat$r_ia32_pat_overlay.ia32_pat$b_pa #endif /* #if !defined(__VAXC) */ typedef struct _ia32_star { int star$l_reserved0_31; /* reserved [0-31] */ unsigned short int star$w_ring0_cs; /* SYSCALL CS/SS [32-47] */ unsigned short int star$w_ring3_cs; /* SYSRET CS/SS [48-63] */ } IA32_STAR; #define MISC_ENABLE$M_FAST_STRINGS_ENABLE 0x1 #define MISC_ENABLE$M_RES1_2 0x6 #define MISC_ENABLE$M_AUTO_THERMAL_ENABLE 0x8 #define MISC_ENABLE$M_RES4_6 0x70 #define MISC_ENABLE$M_PERF_MON_AVAILABLE 0x80 #define MISC_ENABLE$M_RES8_10 0x700 #define MISC_ENABLE$M_BRANCH_TRACE_STORE_U 0x800 #define MISC_ENABLE$M_PEBS 0x1000 #define MISC_ENABLE$M_RES13_15 0xE000 #define MISC_ENABLE$M_ENH_SPEEDSTEP_ENABLE 0x10000 #define MISC_ENABLE$M_RES17 0x20000 #define MISC_ENABLE$M_ENABLE_MONITOR_FSM 0x40000 #define MISC_ENABLE$M_RES19_21 0x380000 #define MISC_ENABLE$M_LIMIT_CPUID_MAXVAL 0x400000 #define MISC_ENABLE$M_XTPR_MESSAGE_DISABLE 0x800000 #define MISC_ENABLE$M_RES24_33 0x3FF000000 #define MISC_ENABLE$M_XD_BIT_DISABLE 0x400000000 #define MISC_ENABLE$M_RES35_63 0xFFFFFFF800000000 typedef struct _misc_enable { /* R/W register */ __union { unsigned __int64 misc_enable$q_quadword; /* The entire quadword */ __struct { unsigned misc_enable$v_fast_strings_enable : 1; /* */ unsigned misc_enable$v_res1_2 : 2; /* Reserved bits [1-2] */ unsigned misc_enable$v_auto_thermal_enable : 1; /* Automatic Thermal [3] */ /* Control Circuit */ /* Enable */ unsigned misc_enable$v_res4_6 : 3; /* Reserved bits [4-6] */ unsigned misc_enable$v_perf_mon_available : 1; /* Performance Monitoring [7] */ /* Available/Enable */ unsigned misc_enable$v_res8_10 : 3; /* Reserved bits [8-10] */ unsigned misc_enable$v_branch_trace_store_u : 1; /* Branch Trace Storage [11] */ /* Unavailable */ unsigned misc_enable$v_pebs : 1; /* Processor Event Based [12] */ /* Sampling Unavailable */ unsigned misc_enable$v_res13_15 : 3; /* Reserved bits [13-15] */ unsigned misc_enable$v_enh_speedstep_enable : 1; /* Enhanced Intel SpeedStep [16] */ /* Technology Enable (R/W) */ unsigned misc_enable$v_res17 : 1; /* Reserved bit [17] */ unsigned misc_enable$v_enable_monitor_fsm : 1; /* Enable Monitor FSM [18] */ unsigned misc_enable$v_res19_21 : 3; /* Reserved bits [19-21] */ unsigned misc_enable$v_limit_cpuid_maxval : 1; /* Limit CPUID Maxval [22] */ unsigned misc_enable$v_xtpr_message_disable : 1; /* xTPR Message Disable [23] */ unsigned misc_enable$v_res24_33 : 10; /* Reserved bits [24-33] */ unsigned misc_enable$v_xd_bit_disable : 1; /* XD Bit Disable [34] */ unsigned misc_enable$v_res35_63 : 29; /* Reserved bits [35-63] */ } misc_enable$r_misc_bits; } misc_enable$r_misc_enable_overlay; } MISC_ENABLE; #if !defined(__VAXC) #define misc_enable$q_quadword misc_enable$r_misc_enable_overlay.misc_enable$q_quadword #define misc_enable$v_fast_strings_enable misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_fast_strings_enab\ le #define misc_enable$v_res1_2 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res1_2 #define misc_enable$v_auto_thermal_enable misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_auto_thermal_enab\ le #define misc_enable$v_res4_6 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res4_6 #define misc_enable$v_perf_mon_available misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_perf_mon_available #define misc_enable$v_res8_10 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res8_10 #define misc_enable$v_branch_trace_store_u misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_branch_trace_sto\ re_u #define misc_enable$v_pebs misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_pebs #define misc_enable$v_res13_15 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res13_15 #define misc_enable$v_enh_speedstep_enable misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_enh_speedstep_en\ able #define misc_enable$v_res17 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res17 #define misc_enable$v_enable_monitor_fsm misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_enable_monitor_fsm #define misc_enable$v_res19_21 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res19_21 #define misc_enable$v_limit_cpuid_maxval misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_limit_cpuid_maxval #define misc_enable$v_xtpr_message_disable misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_xtpr_message_dis\ able #define misc_enable$v_res24_33 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res24_33 #define misc_enable$v_xd_bit_disable misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_xd_bit_disable #define misc_enable$v_res35_63 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res35_63 #endif /* #if !defined(__VAXC) */ #define ARCH_CAP$M_RDCL_NO 0x1 #define ARCH_CAP$M_IBRS_ALL 0x2 #define ARCH_CAP$M_RSBA 0x4 #define ARCH_CAP$M_SKIP_L1DFL_VMENTRY 0x8 #define ARCH_CAP$M_SSB_NO 0x10 #define ARCH_CAP$M_MDS_NO 0x20 #define ARCH_CAP$M_RES6_63 0xFFFFFFFFFFFFFFC0 typedef struct _arch_cap { __union { unsigned __int64 arch_cap$q_quadword; /* Entire quadword */ __struct { unsigned arch_cap$v_rdcl_no : 1; /* Not susceptible to Rogue Data Cache Load [0] */ unsigned arch_cap$v_ibrs_all : 1; /* Indirect Branch Restriction Speculation [1] */ unsigned arch_cap$v_rsba : 1; /* RSB Alternate [2] */ unsigned arch_cap$v_skip_l1dfl_vmentry : 1; /* Hypervisor need not flush L1D on VM entry [3] */ unsigned arch_cap$v_ssb_no : 1; /* Not susceptible to Speculative Store Bypass [4] */ unsigned arch_cap$v_mds_no : 1; /* Not susceptible to Microarchitectural Data Sampling [5] */ #if defined(__VAXC) unsigned arch_cap$v_res6_63_1 : 32; unsigned arch_cap$v_res6_63_2 : 26; #else unsigned __int64 arch_cap$v_res6_63 : 58; /* Reserved bits [6-63] */ #endif } arch_cap$r_arch_bits; } arch_cap$r_arch_cap_overlay; } ARCH_CAP; #if !defined(__VAXC) #define arch_cap$q_quadword arch_cap$r_arch_cap_overlay.arch_cap$q_quadword #define arch_cap$v_rdcl_no arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_rdcl_no #define arch_cap$v_ibrs_all arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_ibrs_all #define arch_cap$v_rsba arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_rsba #define arch_cap$v_skip_l1dfl_vmentry arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_skip_l1dfl_vmentry #define arch_cap$v_ssb_no arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_ssb_no #define arch_cap$v_mds_no arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_mds_no #define arch_cap$v_res6_63 arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_res6_63 #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __X86MSRDEF_LOADED */