/***************************************************************************/ /** **/ /** HPE CONFIDENTIAL. This software is confidential proprietary software **/ /** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/ /** authorized to be used, duplicated OR disclosed to anyone without the **/ /** prior written permission of HPE. **/ /** © 2023 Copyright Hewlett-Packard Enterprise Development, LP **/ /** **/ /** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/ /** proprietary software licensed by VMS Software, Inc., and is not **/ /** authorized to be used, duplicated or disclosed to anyone without **/ /** the prior written permission of VMS Software, Inc. **/ /** © 2023 Copyright VMS Software, Inc. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 9-Nov-2023 12:06:57 by OpenVMS SDL V3.7 */ /* Source: 12-JAN-2021 07:56:50 $1$DGA8345:[LIB_H.SRC]X86HWDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $X86HWDEF ***/ #ifndef __X86HWDEF_LOADED #define __X86HWDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* Registers: */ /* builtins.h defines EFLAGS but not RFLAGS. The 64-bit mode name for this */ /* register is RFLAGS. Define it here temporarily until builtins.h gets */ /* updated. */ #define _X86_REG_RFLAGS 3200 #define RFLG$M_CF 0x1 #define RFLG$M_RES1 0x2 #define RFLG$M_PF 0x4 #define RFLG$M_RES3 0x8 #define RFLG$M_AF 0x10 #define RFLG$M_RES5 0x20 #define RFLG$M_ZF 0x40 #define RFLG$M_SF 0x80 #define RFLG$M_TF 0x100 #define RFLG$M_IF 0x200 #define RFLG$M_DF 0x400 #define RFLG$M_OF 0x800 #define RFLG$M_IOPL 0x3000 #define RFLG$M_NT 0x4000 #define RFLG$M_RES15 0x8000 #define RFLG$M_RF 0x10000 #define RFLG$M_VM 0x20000 #define RFLG$M_AC 0x40000 #define RFLG$M_VIF 0x80000 #define RFLG$M_VIP 0x100000 #define RFLG$M_ID 0x200000 #define RFLG$M_RES22_31 0xFFC00000 typedef struct _rflags { __union { unsigned __int64 rflg$q_quadword; /* The entire quadword */ __struct { unsigned int rflg$l_eflags; /* EFLAGS longword */ unsigned int rflg$l_rsrvd; /* Upper longword reserved */ } rflg$r_eflags_overlay; __struct { unsigned rflg$v_cf : 1; /* CF Carry Flag [0] */ unsigned rflg$v_res1 : 1; /* Reserved bit 1 (MBO) [1] */ unsigned rflg$v_pf : 1; /* PF Parity Flag [2] */ unsigned rflg$v_res3 : 1; /* Reserved bit 3 (MBZ) [3] */ unsigned rflg$v_af : 1; /* Aux Carry Flag [4] */ unsigned rflg$v_res5 : 1; /* Reserved bit 5 (MBZ) [5] */ unsigned rflg$v_zf : 1; /* Zero Flag [6] */ unsigned rflg$v_sf : 1; /* Sign Flag [7] */ unsigned rflg$v_tf : 1; /* Trap Flag [8] */ unsigned rflg$v_if : 1; /* Interrupt Enable Flag [9] */ unsigned rflg$v_df : 1; /* Direction Flag [10] */ unsigned rflg$v_of : 1; /* Overflow Flag [11] */ unsigned rflg$v_iopl : 2; /* I/O Priv Level [12-13] */ unsigned rflg$v_nt : 1; /* Nested Task [14] */ unsigned rflg$v_res15 : 1; /* Reserved bit 15 (MBZ)[15] */ unsigned rflg$v_rf : 1; /* Resume Flag [16] */ unsigned rflg$v_vm : 1; /* Virt-8086 Mode [17] */ unsigned rflg$v_ac : 1; /* Align Check/Acc Ctrl [18] */ unsigned rflg$v_vif : 1; /* Virt Interrupt Flag [19] */ unsigned rflg$v_vip : 1; /* Virt Interrupt Pend [20] */ unsigned rflg$v_id : 1; /* ID Flag [21] */ unsigned rflg$v_res22_31 : 10; /* Reserved (MBZ) [22-31] */ } rflg$r_rflags_bits; } rflg$r_rflags_overlay; } RFLAGS; #if !defined(__VAXC) #define rflg$q_quadword rflg$r_rflags_overlay.rflg$q_quadword #define rflg$l_eflags rflg$r_rflags_overlay.rflg$r_eflags_overlay.rflg$l_eflags #define rflg$l_rsrvd rflg$r_rflags_overlay.rflg$r_eflags_overlay.rflg$l_rsrvd #define rflg$v_cf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_cf #define rflg$v_res1 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res1 #define rflg$v_pf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_pf #define rflg$v_res3 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res3 #define rflg$v_af rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_af #define rflg$v_res5 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res5 #define rflg$v_zf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_zf #define rflg$v_sf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_sf #define rflg$v_tf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_tf #define rflg$v_if rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_if #define rflg$v_df rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_df #define rflg$v_of rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_of #define rflg$v_iopl rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_iopl #define rflg$v_nt rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_nt #define rflg$v_res15 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res15 #define rflg$v_rf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_rf #define rflg$v_vm rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_vm #define rflg$v_ac rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_ac #define rflg$v_vif rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_vif #define rflg$v_vip rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_vip #define rflg$v_id rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_id #define rflg$v_res22_31 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res22_31 #endif /* #if !defined(__VAXC) */ typedef struct _gdtr { unsigned short int gdtr$w_table_limit; /* 16-Bit Table Limit */ unsigned __int64 gdtr$q_lba; /* 64-bit Linear Base Address */ } GDTR; typedef struct _idtr { unsigned short int idtr$w_table_limit; /* 16-Bit Table Limit */ unsigned __int64 idtr$q_lba; /* 64-bit Linear Base Address */ } IDTR; /* */ /* Control Registers */ /* */ /* When loading a control register, reserved bits should always be set */ /* to the values previously read. Otherwise, a General Protection */ /* Fault will occur. */ /* */ #define CR0$M_PE 0x1 #define CR0$M_MP 0x2 #define CR0$M_EM 0x4 #define CR0$M_TS 0x8 #define CR0$M_ET 0x10 #define CR0$M_NE 0x20 #define CR0$M_RES6_15 0xFFC0 #define CR0$M_WP 0x10000 #define CR0$M_RES17 0x20000 #define CR0$M_AM 0x40000 #define CR0$M_RES19_28 0x1FF80000 #define CR0$M_NW 0x20000000 #define CR0$M_CD 0x40000000 #define CR0$M_PG 0x80000000 #define CR0$M_RES32_63 0xFFFFFFFF00000000 typedef struct _cr0 { __union { unsigned __int64 cr0$q_quadword; /* Entire quad register */ __struct { unsigned cr0$v_pe : 1; /* Protection Enable [0] */ unsigned cr0$v_mp : 1; /* Monitor CoProcessor [1] */ unsigned cr0$v_em : 1; /* Emulation [2] */ unsigned cr0$v_ts : 1; /* Task Switched [3] */ unsigned cr0$v_et : 1; /* Extension Type [4] */ unsigned cr0$v_ne : 1; /* Numeric Error [5] */ unsigned cr0$v_res6_15 : 10; /* Reserved [6-15] */ unsigned cr0$v_wp : 1; /* Write Protect [16] */ unsigned cr0$v_res17 : 1; /* Reserved [17] */ unsigned cr0$v_am : 1; /* Alignment Mask [18] */ unsigned cr0$v_res19_28 : 10; /* Reserved [19-28] */ unsigned cr0$v_nw : 1; /* Not Wrt-Thru [29] */ unsigned cr0$v_cd : 1; /* Cache Disable [30] */ unsigned cr0$v_pg : 1; /* Paging [31] */ unsigned cr0$v_res32_63 : 32; /* Reserved MBZ [32-63] */ } cr0$r_cr0_bits; } cr0$r_cr0_overlay; } CR0; #if !defined(__VAXC) #define cr0$q_quadword cr0$r_cr0_overlay.cr0$q_quadword #define cr0$v_pe cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_pe #define cr0$v_mp cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_mp #define cr0$v_em cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_em #define cr0$v_ts cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_ts #define cr0$v_et cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_et #define cr0$v_ne cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_ne #define cr0$v_wp cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_wp #define cr0$v_res17 cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_res17 #define cr0$v_am cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_am #define cr0$v_nw cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_nw #define cr0$v_cd cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_cd #define cr0$v_pg cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_pg #endif /* #if !defined(__VAXC) */ typedef struct _cr2 { __int64 cr2$q_page_fault_address; /* Virtual address that caused */ /* the fault */ } CR2; /* */ /* An attempt to set a reserved bit in CR3 will cause a General Protection Fault */ /* */ #define CR3$M_RES0_2 0x7 #define CR3$M_PWT 0x8 #define CR3$M_PCD 0x10 #define CR3$M_RES5_11 0xFE0 #define CR3$M_PGDIRBASE 0xFFFFFFFFFFFFF000 typedef struct _cr3 { __union { unsigned __int64 cr3$q_quadword; /* Entire quad register */ __struct { unsigned cr3$v_res0_2 : 3; /* Reserved [0-2] */ unsigned cr3$v_pwt : 1; /* Pg-Lvl Write-Thru [3] */ unsigned cr3$v_pcd : 1; /* Pg-Lvl Cache Disable [4] */ unsigned cr3$v_res5_11 : 7; /* Reserved [5-11] */ #if defined(__VAXC) unsigned cr3$v_pgdirbase_1 : 32; unsigned cr3$v_pgdirbase_2 : 20; #else unsigned __int64 cr3$v_pgdirbase : 52; /* Page-Directory Base [12-63] */ #endif } cr3$r_cr3_bits; } cr3$r_cr3_overlay; } CR3; #if !defined(__VAXC) #define cr3$q_quadword cr3$r_cr3_overlay.cr3$q_quadword #define cr3$v_pwt cr3$r_cr3_overlay.cr3$r_cr3_bits.cr3$v_pwt #define cr3$v_pcd cr3$r_cr3_overlay.cr3$r_cr3_bits.cr3$v_pcd #define cr3$v_pgdirbase cr3$r_cr3_overlay.cr3$r_cr3_bits.cr3$v_pgdirbase #endif /* #if !defined(__VAXC) */ /* */ /* An attempt to set a reserved bit in CR4 will cause a General Protection Fault */ /* */ #define CR4$M_VME 0x1 #define CR4$M_PVI 0x2 #define CR4$M_TSD 0x4 #define CR4$M_DE 0x8 #define CR4$M_PSE 0x10 #define CR4$M_PAE 0x20 #define CR4$M_MCE 0x40 #define CR4$M_PGE 0x80 #define CR4$M_PCE 0x100 #define CR4$M_OSFXSR 0x200 #define CR4$M_OSXMMEXCPT 0x400 #define CR4$M_UMIP 0x800 #define CR4$M_LA57 0x1000 #define CR4$M_VMXE 0x2000 #define CR4$M_SMXE 0x4000 #define CR4$M_RES15 0x8000 #define CR4$M_FSGSBASE 0x10000 #define CR4$M_PCIDE 0x20000 #define CR4$M_OSXSAVE 0x40000 #define CR4$M_RES19 0x80000 #define CR4$M_SMEP 0x100000 #define CR4$M_SMAP 0x200000 #define CR4$M_PKE 0x400000 #define CR4$M_RES23_31 0xFF800000 #define CR4$M_RES32_63 0xFFFFFFFF00000000 typedef struct _cr4 { __union { unsigned __int64 cr4$q_quadword; /* Entire quad register */ __struct { unsigned cr4$v_vme : 1; /* Virt-8086 Mode Extensions [0] */ unsigned cr4$v_pvi : 1; /* Prot-mode Virt Interrupts [1] */ unsigned cr4$v_tsd : 1; /* Time Stamp Disable [2] */ unsigned cr4$v_de : 1; /* Debugging Extensions [3] */ unsigned cr4$v_pse : 1; /* Page Size Extensions [4] */ unsigned cr4$v_pae : 1; /* Physical Address Extension [5] */ unsigned cr4$v_mce : 1; /* Machine-Check Enable [6] */ unsigned cr4$v_pge : 1; /* Page Global Enable [7] */ unsigned cr4$v_pce : 1; /* Perf-Monitor Counter Enable [8] */ unsigned cr4$v_osfxsr : 1; /* OS Support: FXSAVE/FXRSTOR [9] */ unsigned cr4$v_osxmmexcpt : 1; /* OS Support: Unmasked SIMD FP Exceptions [10] */ unsigned cr4$v_umip : 1; /* U-Mode Inst Prevention [11] */ unsigned cr4$v_la57 : 1; /* 57-bit linear addresses, [12] */ /* i.e., 5-level paging enabled */ unsigned cr4$v_vmxe : 1; /* VMX-Enable [13] */ unsigned cr4$v_smxe : 1; /* SMX-Enable [14] */ unsigned cr4$v_res15 : 1; /* Reserved [15] */ unsigned cr4$v_fsgsbase : 1; /* FSGSBASE-Enable [16] */ unsigned cr4$v_pcide : 1; /* PCID-Enable [17] */ unsigned cr4$v_osxsave : 1; /* XSAVE & Proc Ext States-Enable [18] */ unsigned cr4$v_res19 : 1; /* Reserved [19] */ unsigned cr4$v_smep : 1; /* Enables super-mode execution prevention [20] */ unsigned cr4$v_smap : 1; /* Enables super-mode access prevention [21] */ unsigned cr4$v_pke : 1; /* Protection-Key-Enable [22] */ unsigned cr4$v_res23_31 : 9; /* Reserved [23-31] */ unsigned cr4$v_res32_63 : 32; /* Reserved MBZ [32-63] */ } cr4$r_cr4_bits; } cr4$r_cr4_overlay; } CR4; #if !defined(__VAXC) #define cr4$q_quadword cr4$r_cr4_overlay.cr4$q_quadword #define cr4$v_vme cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_vme #define cr4$v_pvi cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pvi #define cr4$v_tsd cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_tsd #define cr4$v_de cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_de #define cr4$v_pse cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pse #define cr4$v_pae cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pae #define cr4$v_mce cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_mce #define cr4$v_pge cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pge #define cr4$v_pce cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pce #define cr4$v_osfxsr cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_osfxsr #define cr4$v_osxmmexcpt cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_osxmmexcpt #define cr4$v_umip cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_umip #define cr4$v_la57 cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_la57 #define cr4$v_vmxe cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_vmxe #define cr4$v_smxe cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_smxe #define cr4$v_fsgsbase cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_fsgsbase #define cr4$v_pcide cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pcide #define cr4$v_osxsave cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_osxsave #define cr4$v_smep cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_smep #define cr4$v_smap cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_smap #define cr4$v_pke cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pke #endif /* #if !defined(__VAXC) */ /* */ /* An attempt to set a reserved bit in CR8 will cause a General Protection Fault */ /* */ #define CR8$M_TPL 0xF #define CR8$M_RES_4_63 0xFFFFFFFFFFFFFFF0 typedef struct _cr8 { __union { unsigned __int64 cr8$q_quadword; /* Entire quad register */ __struct { unsigned cr8$v_tpl : 4; /* Task Priority Level [0-3] */ unsigned cr8$v_res_4_63_1 : 32; unsigned cr8$v_res_4_63_2 : 32; /* Reserved MBZ [3-63] */ unsigned cr8$v_fill_0_ : 4; } cr8$r_cr8_bits; } cr8$r_cr8_overlay; } CR8; #if !defined(__VAXC) #define cr8$q_quadword cr8$r_cr8_overlay.cr8$q_quadword #define cr8$v_tpl cr8$r_cr8_overlay.cr8$r_cr8_bits.cr8$v_tpl #endif /* #if !defined(__VAXC) */ #define XCR0$M_X87_FPU_MMX 0x1 #define XCR0$M_SSE 0x2 #define XCR0$M_AVX 0x4 #define XCR0$M_BNDREG 0x8 #define XCR0$M_BNDCSR 0x10 #define XCR0$M_OPMASK 0x20 #define XCR0$M_ZMM_HI256 0x40 #define XCR0$M_HI16_ZMM 0x80 #define XCR0$M_RES8 0x100 #define XCR0$M_PKRU 0x200 #define XCR0$M_RES10_62 0x7FFFFFFFFFFFFC00 #define XCR0$M_RES63 0x8000000000000000 typedef struct _xcr0 { __union { unsigned __int64 xcr0$q_quadword; /* Entire quad register */ __struct { unsigned xcr0$v_x87_fpu_mmx : 1; /* x87 FPU/MMX state MBO [0] */ unsigned xcr0$v_sse : 1; /* SSE state [1] */ unsigned xcr0$v_avx : 1; /* AVX state [2] */ unsigned xcr0$v_bndreg : 1; /* BNDREG state [3] */ unsigned xcr0$v_bndcsr : 1; /* BNDCSR state [4] */ unsigned xcr0$v_opmask : 1; /* OPMASK state [5] */ unsigned xcr0$v_zmm_hi256 : 1; /* ZMM_Hi256 state [6] */ unsigned xcr0$v_hi16_zmm : 1; /* Hi16_ZMM state [7] */ unsigned xcr0$v_res8 : 1; /* Reserved [8] */ unsigned xcr0$v_pkru : 1; /* BNDREG state [9] */ unsigned xcr0$v_res10_62_1 : 32; unsigned xcr0$v_res10_62_2 : 21; /* Reserved for future state [10-62] */ unsigned xcr0$v_res63 : 1; /* Reserved for bit vec expansion [63] */ } xcr0$r_xcr0_bits; } xcr0$r_xcr0_overlay; } XCR0; #if !defined(__VAXC) #define xcr0$q_quadword xcr0$r_xcr0_overlay.xcr0$q_quadword #define xcr0$v_x87_fpu_mmx xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_x87_fpu_mmx #define xcr0$v_sse xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_sse #define xcr0$v_avx xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_avx #define xcr0$v_bndreg xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_bndreg #define xcr0$v_bndcsr xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_bndcsr #define xcr0$v_opmask xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_opmask #define xcr0$v_zmm_hi256 xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_zmm_hi256 #define xcr0$v_hi16_zmm xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_hi16_zmm #define xcr0$v_res8 xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_res8 #define xcr0$v_pkru xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_pkru #endif /* #if !defined(__VAXC) */ #define MXCSR$M_IE 0x1 #define MXCSR$M_DE 0x2 #define MXCSR$M_ZE 0x4 #define MXCSR$M_OE 0x8 #define MXCSR$M_UE 0x10 #define MXCSR$M_PE 0x20 #define MXCSR$M_DAZ 0x40 #define MXCSR$M_IM 0x80 #define MXCSR$M_DM 0x100 #define MXCSR$M_ZM 0x200 #define MXCSR$M_OM 0x400 #define MXCSR$M_UM 0x800 #define MXCSR$M_PM 0x1000 #define MXCSR$M_RC 0x6000 #define MXCSR$M_FZ 0x8000 #define MXCSR$M_RES16_31 0xFFFF0000 #define MXCSR$M_RES32_63 0xFFFFFFFF00000000 typedef struct _mxcsr { __union { unsigned __int64 mxcsr$q_quadword; /* Entire register */ __struct { unsigned mxcsr$v_ie : 1; /* Invalid operation flag [0] */ unsigned mxcsr$v_de : 1; /* Denormal flag [1] */ unsigned mxcsr$v_ze : 1; /* Divide-by-zero flag [2] */ unsigned mxcsr$v_oe : 1; /* Overflow flag [3] */ unsigned mxcsr$v_ue : 1; /* Underflow flag [4] */ unsigned mxcsr$v_pe : 1; /* Precision flag [5] */ unsigned mxcsr$v_daz : 1; /* Denormals are zeros [6] */ unsigned mxcsr$v_im : 1; /* Invalid operation mask [7] */ unsigned mxcsr$v_dm : 1; /* Denormal mask [8] */ unsigned mxcsr$v_zm : 1; /* Divide-by-zero mask [9] */ unsigned mxcsr$v_om : 1; /* Overflow mask [10] */ unsigned mxcsr$v_um : 1; /* Underflow mask [11] */ unsigned mxcsr$v_pm : 1; /* Precision mask [12] */ unsigned mxcsr$v_rc : 2; /* Rounding Control [13-14] */ unsigned mxcsr$v_fz : 1; /* Flush to Zero [15] */ unsigned mxcsr$v_res16_31 : 16; /* Reserved [16-31] */ unsigned mxcsr$v_res32_63 : 32; /* Fill out to 64 bits [32-63] */ } mxcsr$r_mxcsr_bits; } mxcsr$r_mxcsr_overlay; } MXCSR; #if !defined(__VAXC) #define mxcsr$q_quadword mxcsr$r_mxcsr_overlay.mxcsr$q_quadword #define mxcsr$v_ie mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_ie #define mxcsr$v_de mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_de #define mxcsr$v_ze mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_ze #define mxcsr$v_oe mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_oe #define mxcsr$v_ue mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_ue #define mxcsr$v_pe mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_pe #define mxcsr$v_daz mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_daz #define mxcsr$v_im mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_im #define mxcsr$v_dm mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_dm #define mxcsr$v_zm mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_zm #define mxcsr$v_om mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_om #define mxcsr$v_um mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_um #define mxcsr$v_pm mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_pm #define mxcsr$v_rc mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_rc #define mxcsr$v_fz mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_fz #endif /* #if !defined(__VAXC) */ /* Model Specific Registers (MSRs): */ /* Segment Descriptors */ #define SEGD$M_TYPE 0xF #define SEGD$M_S 0x10 #define SEGD$M_DPL 0x60 #define SEGD$M_P 0x80 #define SEGD$M_LIMIT_HIGH 0xF00 #define SEGD$M_AVL 0x1000 #define SEGD$M_L 0x2000 #define SEGD$M_D_B 0x4000 #define SEGD$M_G 0x8000 typedef struct _segd { unsigned short int segd$w_limit_low; /* Segment Limit 15:00 */ unsigned short int segd$w_base_addr_low; /* Base Address 15:00 */ unsigned char segd$b_base_addr_mid; /* Base Address 23:16 [0-7] */ __union { unsigned short int segd$w_ignore; /* Overlays Bit fields below */ __struct { unsigned segd$v_type : 4; /* Type [8-11] */ unsigned segd$v_s : 1; /* Desc type (0 = system; [12] */ /* 1 = code or data) */ unsigned segd$v_dpl : 2; /* Descriptor Privilege Level [13-14] */ unsigned segd$v_p : 1; /* Segment Present [15] */ unsigned segd$v_limit_high : 4; /* Segment Limit 19:16 [16-19] */ unsigned segd$v_avl : 1; /* Available for system software [20] */ unsigned segd$v_l : 1; /* 64-bit code segment [21] */ unsigned segd$v_d_b : 1; /* Default operation size [22] */ /* (0 = 16-bit segment; 1 = 32-bit segment) */ unsigned segd$v_g : 1; /* Granularity [23] */ } segd$r_tss_fields; } segd$r_tss_fields_ovrlay; unsigned char segd$b_base_addr_hi; /* Base Address 31:24 [24-31] */ } SEGD; #if !defined(__VAXC) #define segd$v_type segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_type #define segd$v_s segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_s #define segd$v_dpl segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_dpl #define segd$v_p segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_p #define segd$v_limit_high segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_limit_high #define segd$v_avl segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_avl #define segd$v_l segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_l #define segd$v_d_b segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_d_b #define segd$v_g segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_g #endif /* #if !defined(__VAXC) */ #define IDTD$M_IST 0x7 #define IDTD$M_MBZ3 0x8 #define IDTD$M_MBZ4 0x10 #define IDTD$M_MBZ5_7 0xE0 #define IDTD$M_TYPE 0xF00 #define IDTD$M_MBZ12 0x1000 #define IDTD$M_DPL 0x6000 #define IDTD$M_P 0x8000 typedef struct _idtd { __union { unsigned __int64 idtd$q_quadword1; __struct { unsigned short int idtd$w_offset_low; /* Offset 15..0 */ unsigned short int idtd$w_selector; /* Segment Selector for destination code segment */ __struct { unsigned idtd$v_ist : 3; /* Interrupt Stack Table [0-2] */ unsigned idtd$v_mbz3 : 1; /* Must Be Zero [3] */ unsigned idtd$v_mbz4 : 1; /* Must Be Zero [4] */ unsigned idtd$v_mbz5_7 : 3; /* Must Be Zero [5-7] */ unsigned idtd$v_type : 4; /* Type [8-11] */ unsigned idtd$v_mbz12 : 1; /* Must Be Zero [12] */ unsigned idtd$v_dpl : 2; /* Descriptor Privilege Level [13-14] */ unsigned idtd$v_p : 1; /* Segment Present flag [15] */ } idtd$r_idt64_fields; unsigned short int idtd$w_offset_mid; /* Offset 31..16 */ } idtd$r_qw1_fields; } idtd$r_qw1_overlay; __union { unsigned __int64 idtd$q_quadword2; __struct { unsigned int idtd$l_offset_hi; /* Offset 63..32 */ unsigned int idtd$l_reserved; /* Reserved */ } idtd$r_qw2_fields; } idtd$r_qw2_overlay; } IDTD; #if !defined(__VAXC) #define idtd$q_quadword1 idtd$r_qw1_overlay.idtd$q_quadword1 #define idtd$w_offset_low idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$w_offset_low #define idtd$w_selector idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$w_selector #define idtd$v_ist idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$r_idt64_fields.idtd$v_ist #define idtd$v_type idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$r_idt64_fields.idtd$v_type #define idtd$v_dpl idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$r_idt64_fields.idtd$v_dpl #define idtd$v_p idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$r_idt64_fields.idtd$v_p #define idtd$w_offset_mid idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$w_offset_mid #define idtd$q_quadword2 idtd$r_qw2_overlay.idtd$q_quadword2 #define idtd$l_offset_hi idtd$r_qw2_overlay.idtd$r_qw2_fields.idtd$l_offset_hi #endif /* #if !defined(__VAXC) */ #define IDTD$C_LENGTH 16 /* X86 interrupt vectors */ #define X86_IDT$C_DE 0 /* 0 Divide error */ #define X86_IDT$C_DB 1 /* 1 Debug */ #define X86_IDT$C_NMI 2 /* 2 Non-Maskable Interrupt */ #define X86_IDT$C_BP 3 /* 3 Breakpoint */ #define X86_IDT$C_OF 4 /* 4 Integer overflow */ #define X86_IDT$C_BR 5 /* 5 Bound range exceeded */ #define X86_IDT$C_UD 6 /* 6 Invalid opcode */ #define X86_IDT$C_NM 7 /* 7 No math */ #define X86_IDT$C_DF 8 /* 8 Double fault */ #define X86_IDT$C_RSV_9 9 /* 9 Reserved */ #define X86_IDT$C_TS 10 /* 10 Invalid TSS */ #define X86_IDT$C_NP 11 /* 11 Segment not present */ #define X86_IDT$C_SS 12 /* 12 Stack segment fault */ #define X86_IDT$C_GP 13 /* 13 General protection fault */ #define X86_IDT$C_PF 14 /* 14 Page fault */ #define X86_IDT$C_RSV_15 15 /* 15 Reserved */ #define X86_IDT$C_MF 16 /* 16 Math fault */ #define X86_IDT$C_AC 17 /* 17 Alignment check */ #define X86_IDT$C_MC 18 /* 18 Machine check exception */ #define X86_IDT$C_XM 19 /* 19 SIMD Floating point exception */ #define X86_IDT$C_VE 20 /* 20 Virtualization exception */ #define X86_IDT$C_CP 21 /* 21 Control Protection Exception */ #define X86_IDT$C_RSV_22 22 /* 22 Reserved */ #define X86_IDT$C_RSV_23 23 /* 23 Reserved */ #define X86_IDT$C_RSV_24 24 /* 24 Reserved */ #define X86_IDT$C_RSV_25 25 /* 25 Reserved */ #define X86_IDT$C_RSV_26 26 /* 26 Reserved */ #define X86_IDT$C_RSV_27 27 /* 27 Reserved */ #define X86_IDT$C_RSV_28 28 /* 28 Reserved */ #define X86_IDT$C_VC 29 /* 29 VMM Comm Exception */ #define X86_IDT$C_SX 30 /* 30 Security exception */ #define X86_IDT$C_RSV_31 31 /* 31 Reserved */ #define X86_IDT$C_BREAK 32 /* 32 */ #define X86_IDT$C_HW_START 33 /* 33 is first hardware interrupt */ /* TSS (or LDT) Descriptor. */ #define TSSD$M_TYPE 0xF #define TSSD$M_MBZ9 0x10 #define TSSD$M_DPL 0x60 #define TSSD$M_P 0x80 #define TSSD$M_LIMIT_HIGH 0xF00 #define TSSD$M_AVL 0x1000 #define TSSD$M_MBZ21 0x2000 #define TSSD$M_MBZ22 0x4000 #define TSSD$M_G 0x8000 #define TSSD$M_RESERVED0_7 0xFF #define TSSD$M_MBZ8_12 0x1F00 #define TSSD$M_RESERVED13_31 0xFFFFE000 typedef struct _tssd { unsigned short int tssd$w_limit_low; /* Segment Limit 15:00 */ unsigned short int tssd$w_base_addr_low; /* Base Address 15:00 */ unsigned char tssd$b_base_addr_mid1; /* Base Address 23:16 [0-7] */ __union { unsigned short int tssd$w_ignore; /* Overlays Bit fields below */ __struct { unsigned tssd$v_type : 4; /* Type [8-11] */ unsigned tssd$v_mbz9 : 1; /* MBZ [12] */ unsigned tssd$v_dpl : 2; /* Descriptor Privilege Level [13-14] */ unsigned tssd$v_p : 1; /* Segment Present [15] */ unsigned tssd$v_limit_high : 4; /* Segment Limit 19:16 [16-19] */ unsigned tssd$v_avl : 1; /* Available for system software [20] */ unsigned tssd$v_mbz21 : 1; /* MBZ [21] */ unsigned tssd$v_mbz22 : 1; /* MBZ [22] */ unsigned tssd$v_g : 1; /* Granularity [23] */ } tssd$r_tss_fields; } tssd$r_tss_fields_ovrlay; unsigned char tssd$b_base_addr_mid2; /* Base Address 31:24 [24-31] */ unsigned int tssd$l_base_addr_hi; /* Base Address 63:32 */ __struct { unsigned tssd$v_reserved0_7 : 8; /* Reserved [0-7] */ unsigned tssd$v_mbz8_12 : 5; /* Must Be Zero [8-12] */ unsigned tssd$v_reserved13_31 : 19; /* Reserved [13-31] */ } tssd$r_reserved_fields; } TSSD; #if !defined(__VAXC) #define tssd$v_type tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_type #define tssd$v_dpl tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_dpl #define tssd$v_p tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_p #define tssd$v_limit_high tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_limit_high #define tssd$v_avl tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_avl #define tssd$v_g tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_g #define tssd$v_reserved0_7 tssd$r_reserved_fields.tssd$v_reserved0_7 #define tssd$v_mbz8_12 tssd$r_reserved_fields.tssd$v_mbz8_12 #define tssd$v_reserved13_31 tssd$r_reserved_fields.tssd$v_reserved13_31 #endif /* #if !defined(__VAXC) */ /* Page Fault Exception Error Code definitions */ #define ERRC$M_P 0x1 #define ERRC$M_RW 0x2 #define ERRC$M_US 0x4 #define ERRC$M_R 0x8 #define ERRC$M_I 0x10 typedef struct _error_code { __union { unsigned __int64 errc$q_quadword; /* The entire quadword */ __struct { unsigned errc$v_p : 1; /* Present => 1 [0] */ unsigned errc$v_rw : 1; /* Write => 1 [1] */ unsigned errc$v_us : 1; /* User => 1 [2] */ unsigned errc$v_r : 1; /* Reserved bit set => 1 [3] */ unsigned errc$v_i : 1; /* Instruction fetch => 1 [4] */ unsigned errc$v_fill_1_ : 3; } errc$r_error_code_bits; } errc$r_error_code_overlay; } ERROR_CODE; #if !defined(__VAXC) #define errc$q_quadword errc$r_error_code_overlay.errc$q_quadword #define errc$v_p errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_p #define errc$v_rw errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_rw #define errc$v_us errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_us #define errc$v_r errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_r #define errc$v_i errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_i #endif /* #if !defined(__VAXC) */ typedef struct _xmmreg { unsigned __int64 xmm$q_lowpart; unsigned __int64 xmm$q_highpart; } XMMREG; typedef struct _stmreg { unsigned __int64 stm$q_lowpart; unsigned short int stm$w_highpart; unsigned char stm$b_resvd [6]; } STMREG; typedef struct _xsave { unsigned short int xsv$w_fcw; /* FPU Control Word */ unsigned short int xsv$w_fsw; /* FPU Status Word */ unsigned short int xsv$w_ftw; /* FPU Tag Word + rsvd byte */ unsigned short int xsv$w_fop; /* FPU Opcode */ __union { __struct { unsigned __int64 xsv$q_rip; /* FPU Instruction Pointer */ unsigned __int64 xsv$q_rdp; /* FPU Data Pointer */ } xsv$r_rregs; __struct { unsigned int xsv$l_fip; /* FPU IP Offset */ unsigned int xsv$l_fcs; /* FPU IP Selector */ unsigned int xsv$l_foo; /* FPU Operand Offset */ unsigned int xsv$l_fos; /* FPU Operand Selector */ } xsv$r_fregs; } xsv$r_fpureg_overlay; unsigned int xsv$l_mxcsr; /* MXCSR Register State */ unsigned int xsv$l_mxcsr_mask; /* MXCSR Mask */ STMREG xsv$r_st_regs [8]; /* 8x 10-byte STx/MMx + 6-byte rsvd */ XMMREG xsv$r_xmm_regs [16]; /* 16x 16-byte XMMx */ unsigned __int64 xsv$q_resvd [12]; /* Part padding part reserved */ } XSAVE; #if !defined(__VAXC) #define xsv$q_rip xsv$r_fpureg_overlay.xsv$r_rregs.xsv$q_rip #define xsv$q_rdp xsv$r_fpureg_overlay.xsv$r_rregs.xsv$q_rdp #define xsv$l_fip xsv$r_fpureg_overlay.xsv$r_fregs.xsv$l_fip #define xsv$l_fcs xsv$r_fpureg_overlay.xsv$r_fregs.xsv$l_fcs #define xsv$l_foo xsv$r_fpureg_overlay.xsv$r_fregs.xsv$l_foo #define xsv$l_fos xsv$r_fpureg_overlay.xsv$r_fregs.xsv$l_fos #endif /* #if !defined(__VAXC) */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __X86HWDEF_LOADED */