/***************************************************************************/ /** **/ /** HPE CONFIDENTIAL. This software is confidential proprietary software **/ /** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/ /** authorized to be used, duplicated OR disclosed to anyone without the **/ /** prior written permission of HPE. **/ /** © 2023 Copyright Hewlett-Packard Enterprise Development, LP **/ /** **/ /** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/ /** proprietary software licensed by VMS Software, Inc., and is not **/ /** authorized to be used, duplicated or disclosed to anyone without **/ /** the prior written permission of VMS Software, Inc. **/ /** © 2023 Copyright VMS Software, Inc. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 9-Nov-2023 12:06:48 by OpenVMS SDL V3.7 */ /* Source: 08-SEP-2003 12:18:59 $1$DGA8345:[LIB_H.SRC]SPPADEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $SPPADEF ***/ #ifndef __SPPADEF_LOADED #define __SPPADEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #define PDIR$M_VINDEX 0xFF #define PDIR$M_SV 0x800 #define PDIR$M_V 0x8000000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sppa_io_pdir { #pragma __nomember_alignment unsigned pdir$v_vindex : 8; /* Virtual index 0xFF on Itanium */ unsigned pdir$v_reserved_pdir_1 : 3; /* Reserved */ unsigned pdir$v_sv : 1; /* Swap control field is valid */ #if defined(__VAXC) unsigned pdir$v_ppn_1 : 32; unsigned pdir$v_ppn_2 : 11; #else unsigned __int64 pdir$v_ppn : 43; /* Physical Page number (PFN) */ #endif unsigned pdir$v_swap_ctrl : 8; /* Swap control field (documentation?) */ unsigned pdir$v_v : 1; /* Valid PDIR entry */ } SPPA_IO_PDIR; #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sppa_func_hdr { #pragma __nomember_alignment __union { unsigned __int64 sppa$q_func_id; /* 000 Function Id */ __struct { __struct { /* v- PCI Config Space Offset */ unsigned short int sppa$w_vendor_id; /* 00 HP is 103C */ unsigned short int sppa$w_function_id; /* 02 Unique w/in Vendor */ unsigned short int sppa$w_control; /* 04 See PCI Spec */ unsigned short int sppa$w_status; /* 06 See PCI spec */ } sppa$r_fill_func_id; } sppa$r_fill_1_; } sppa$r_fill_0_; __union { unsigned __int64 sppa$q_func_class; /* 008 Function Class */ __struct { __struct { /* v- PCI Config Space Offset */ unsigned char sppa$b_revision; /* 08 Rev w/in Function ID */ unsigned char sppa$b_interface; /* 09 Class Code - Interface */ unsigned char sppa$b_sub_class; /* 0A Class Code - Subclass */ unsigned char sppa$b_base_class; /* 0B Class Code - Base Class */ } sppa$r_fill_func_class; } sppa$r_fill_3_; } sppa$r_fill_2_; } SPPA_FUNC_HDR; #if !defined(__VAXC) #define sppa$q_func_id sppa$r_fill_0_.sppa$q_func_id #define sppa$w_vendor_id sppa$r_fill_0_.sppa$r_fill_1_.sppa$r_fill_func_id.sppa$w_vendor_id #define sppa$w_function_id sppa$r_fill_0_.sppa$r_fill_1_.sppa$r_fill_func_id.sppa$w_function_id #define sppa$w_control sppa$r_fill_0_.sppa$r_fill_1_.sppa$r_fill_func_id.sppa$w_control #define sppa$w_status sppa$r_fill_0_.sppa$r_fill_1_.sppa$r_fill_func_id.sppa$w_status #define sppa$q_func_class sppa$r_fill_2_.sppa$q_func_class #define sppa$b_revision sppa$r_fill_2_.sppa$r_fill_3_.sppa$r_fill_func_class.sppa$b_revision #define sppa$b_interface sppa$r_fill_2_.sppa$r_fill_3_.sppa$r_fill_func_class.sppa$b_interface #define sppa$b_sub_class sppa$r_fill_2_.sppa$r_fill_3_.sppa$r_fill_func_class.sppa$b_sub_class #define sppa$b_base_class sppa$r_fill_2_.sppa$r_fill_3_.sppa$r_fill_func_class.sppa$b_base_class #endif /* #if !defined(__VAXC) */ #define SPPA$M_IM 0x8000 #define SPPA$M_CONTROL_RF 0x1 #define SPPA$M_CONTROL_FF 0x2 #define SPPA$M_CONTROL_RV 0x4 #define SPPA$M_CONTROL_CL 0x8 #define SPPA$M_CONTROL_CE 0x10 #define SPPA$M_CONTROL_HF 0x20 #define SPPA$M_STATUS_RC 0x80000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sppa_mod_status { #pragma __nomember_alignment __union { unsigned __int64 sppa$q_mod_info; /* 100 Module Information */ __struct { __struct { unsigned sppa$v_physical_id : 15; /* Unique Module ID */ unsigned sppa$v_im : 1; /* Implementation-dependent */ unsigned short int sppa$w_functions_present; /* Functions present mask; F0 MBO */ char sppa$b_reserved_mod_info_1 [4]; /* Reserved */ } sppa$r_fill_mod_info; } sppa$r_fill_5_; } sppa$r_fill_4_; __union { unsigned __int64 sppa$q_status_control; /* 108 Status/Control Info */ __struct { __struct { unsigned sppa$v_control_rf : 1; /* Resets Function */ unsigned sppa$v_control_ff : 1; /* Forwards Firmware Xactions (?) */ unsigned sppa$v_control_rv : 1; /* Reserved */ unsigned sppa$v_control_cl : 1; /* Clear Error Logging */ unsigned sppa$v_control_ce : 1; /* Enable Error Log Clearing */ unsigned sppa$v_control_hf : 1; /* Hard Fail Enable */ unsigned sppa$v_reserved_hdr_2 : 25; /* Reserved */ unsigned sppa$v_status_rc : 1; /* Reset-in-progress if set */ unsigned sppa$v_reserved_hdr_3 : 31; /* Reserved */ unsigned sppa$v_fill_8_ : 1; } sppa$r_fill_status_control; } sppa$r_fill_7_; } sppa$r_fill_6_; } SPPA_MOD_STATUS; #if !defined(__VAXC) #define sppa$q_mod_info sppa$r_fill_4_.sppa$q_mod_info #define sppa$v_physical_id sppa$r_fill_4_.sppa$r_fill_5_.sppa$r_fill_mod_info.sppa$v_physical_id #define sppa$v_im sppa$r_fill_4_.sppa$r_fill_5_.sppa$r_fill_mod_info.sppa$v_im #define sppa$w_functions_present sppa$r_fill_4_.sppa$r_fill_5_.sppa$r_fill_mod_info.sppa$w_functions_present #define sppa$q_status_control sppa$r_fill_6_.sppa$q_status_control #define sppa$v_control_rf sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_rf #define sppa$v_control_ff sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_ff #define sppa$v_control_rv sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_rv #define sppa$v_control_cl sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_cl #define sppa$v_control_ce sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_ce #define sppa$v_control_hf sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_hf #define sppa$v_status_rc sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_status_rc #endif /* #if !defined(__VAXC) */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sppa_sba_map { #pragma __nomember_alignment SPPA_FUNC_HDR sba$r_sba_hdr; char sba$b_reserved_sba_1 [240]; /* */ SPPA_MOD_STATUS sba$r_sba_mod; char sba$b_reserved_sba_end [3824]; /* Pad to 4K */ } SPPA_SBA_MAP; #define SPPA$S_SPPA_SBA_MAP_LENGTH 4096 #define IOC$M_RE 0x1 #define IOC$K_TS_4K 0 /* 4K Page Size */ #define IOC$K_TS_8K 1 /* 8K Page Size */ #define IOC$K_TS_16K 2 /* 16K Page Size */ #define IOC$K_TS_64K 3 /* 64K Page Size */ #define IOC$M_CTRL_FLUSH_CACHE 0x400 #define IOC$M_CTRL_IOCB_EMPTY 0x800 #define IOC$M_FLUSH_CACHE 0x1 #define IOC$M_FLUSH_2_CLEAN 0x2 #define IOC$M_FLUSH_ALL_CURRENT 0x4 #define IOC$M_PR_PLUNGE 0x8 #define IOC$M_FIP_SNAP 0x10 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sppa_ioc_map { #pragma __nomember_alignment unsigned __int64 ioc$q_func_id; char ioc$b_reserved_ioc_0 [248]; /* */ unsigned __int64 ioc$q_mod_info; char ioc$b_reserved_ioc_1 [248]; unsigned __int64 ioc$q_lba_port0_cntrl; /* 200 LBA 0 Port Control */ unsigned __int64 ioc$q_lba_port1_cntrl; /* 208 LBA 1 Port Control */ unsigned __int64 ioc$q_lba_port2_cntrl; /* 210 LBA 2 Port Control */ unsigned __int64 ioc$q_lba_port3_cntrl; /* 218 LBA 3 Port Control */ unsigned __int64 ioc$q_lba_port4_cntrl; /* 220 LBA 4 Port Control */ unsigned __int64 ioc$q_lba_port5_cntrl; /* 228 LBA 5 Port Control */ unsigned __int64 ioc$q_lba_port6_cntrl; /* 230 LBA 6 Port Control */ unsigned __int64 ioc$q_lba_port7_cntrl; /* 238 LBA 7 Port Control */ char ioc$b_reserved_ioc_2 [192]; __union { unsigned __int64 ioc$q_ibase; /* 300 Base of IOV Space */ __struct { __struct { unsigned ioc$v_re : 1; /* Enable Mapping on Range */ unsigned ioc$v_fill_21_ : 7; } ioc$r_fill_ibase_bits; } ioc$r_fill_10_; } ioc$r_fill_9_; unsigned __int64 ioc$q_imask; /* 308 Mask/Size of IOV Space */ __union { unsigned __int64 ioc$q_pcom; /* 310 Purge Command */ __struct { __struct { unsigned ioc$v_size : 5; /* Naturally Aligned Purge Size */ unsigned ioc$v_pcom_reserved_ioc_1 : 7; unsigned ioc$v_purge_addr : 20; /* Address Range to be Purged */ } ioc$r_fill_pcom_bits; } ioc$r_fill_12_; } ioc$r_fill_11_; __union { unsigned __int64 ioc$q_tcnfg; /* 318 IOTLB Configuration */ __struct { __struct { unsigned ioc$v_ts : 2; /* TLB Page Size Code */ unsigned ioc$v_fill_22_ : 6; } ioc$r_fill_tcnfg_bits; } ioc$r_fill_14_; } ioc$r_fill_13_; __union { unsigned __int64 ioc$q_pdir; /* 320 Physical Addr of IOTLB */ __struct { __struct { unsigned ioc$v_pdir_reserved_ioc_1 : 12; unsigned ioc$v_pdir_base : 32; /* IOTLB PA bit extent */ unsigned ioc$v_fill_23_ : 4; } ioc$r_fill_pdir_bits; } ioc$r_fill_16_; } ioc$r_fill_15_; char ioc$b_reserved_ioc_3 [216]; __union { unsigned __int64 ioc$q_flush_ctrl; /* 400 Flush/IKE compatibility */ __struct { __struct { unsigned ioc$v_flush_ctrl_reserved_ioc_1 : 10; unsigned ioc$v_ctrl_flush_cache : 1; /* Flush entire cache, then reset */ unsigned ioc$v_ctrl_iocb_empty : 1; /* Set when IOC buffer is empty */ unsigned ioc$v_fill_24_ : 4; } ioc$r_fill_flush_ctrl_bits; } ioc$r_fill_18_; } ioc$r_fill_17_; char ioc$b_reserved_ioc_4 [32]; __union { unsigned __int64 ioc$q_flush_command; /* 428 Flush Command */ __struct { __struct { unsigned ioc$v_flush_cache : 1; /* Flush entire cache, then reset */ unsigned ioc$v_flush_2_clean : 1; /* Flush dirty cache lines, then reset */ unsigned ioc$v_flush_all_current : 1; /* Flush all read_current lines, then reset */ unsigned ioc$v_pr_plunge : 1; /* Kinky */ unsigned ioc$v_fip_snap : 1; /* Snapshot */ unsigned ioc$v_fill_25_ : 3; } ioc$r_fill_flush_command_bits; } ioc$r_fill_20_; } ioc$r_fill_19_; char ioc$b_reserved_ioc_5 [40]; unsigned __int64 ioc$q_cache_fip_snap; /* 458 Fetch-In-Progress Mask */ char ioc$b_reserved_ioc_6 [1520]; unsigned __int64 ioc$q_lba_port8_cntrl; /* A50 LBA 8 Port Control */ unsigned __int64 ioc$q_lba_port9_cntrl; /* A58 LBA 9 Port Control */ unsigned __int64 ioc$q_lba_port10_cntrl; /* A60 LBA 10 Port Control */ unsigned __int64 ioc$q_lba_port11_cntrl; /* A68 LBA 11 Port Control */ unsigned __int64 ioc$q_lba_port12_cntrl; /* A70 LBA 12 Port Control */ unsigned __int64 ioc$q_lba_port13_cntrl; /* A78 LBA 13 Port Control */ unsigned __int64 ioc$q_lba_port14_cntrl; /* A80 LBA 14 Port Control */ unsigned __int64 ioc$q_lba_port15_cntrl; /* A88 LBA 15 Port Control */ char ioc$b_reserved_ioc_end [1392]; /* Pad to 4K */ } SPPA_IOC_MAP; #if !defined(__VAXC) #define ioc$q_ibase ioc$r_fill_9_.ioc$q_ibase #define ioc$v_re ioc$r_fill_9_.ioc$r_fill_10_.ioc$r_fill_ibase_bits.ioc$v_re #define ioc$q_pcom ioc$r_fill_11_.ioc$q_pcom #define ioc$v_size ioc$r_fill_11_.ioc$r_fill_12_.ioc$r_fill_pcom_bits.ioc$v_size #define ioc$v_purge_addr ioc$r_fill_11_.ioc$r_fill_12_.ioc$r_fill_pcom_bits.ioc$v_purge_addr #define ioc$q_tcnfg ioc$r_fill_13_.ioc$q_tcnfg #define ioc$v_ts ioc$r_fill_13_.ioc$r_fill_14_.ioc$r_fill_tcnfg_bits.ioc$v_ts #define ioc$q_pdir ioc$r_fill_15_.ioc$q_pdir #define ioc$v_pdir_base ioc$r_fill_15_.ioc$r_fill_16_.ioc$r_fill_pdir_bits.ioc$v_pdir_base #define ioc$q_flush_ctrl ioc$r_fill_17_.ioc$q_flush_ctrl #define ioc$v_ctrl_flush_cache ioc$r_fill_17_.ioc$r_fill_18_.ioc$r_fill_flush_ctrl_bits.ioc$v_ctrl_flush_cache #define ioc$v_ctrl_iocb_empty ioc$r_fill_17_.ioc$r_fill_18_.ioc$r_fill_flush_ctrl_bits.ioc$v_ctrl_iocb_empty #define ioc$q_flush_command ioc$r_fill_19_.ioc$q_flush_command #define ioc$v_flush_cache ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_flush_cache #define ioc$v_flush_2_clean ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_flush_2_clean #define ioc$v_flush_all_current ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_flush_all_current #define ioc$v_pr_plunge ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_pr_plunge #define ioc$v_fip_snap ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_fip_snap #endif /* #if !defined(__VAXC) */ #define SPPA$S_SPPA_IOC_MAP_LENGTH 4096 #define SPPA$M_ENABLE_ARB 0x1 #define SPPA$M_MASK_A 0x2 #define SPPA$M_MASK_B 0x4 #define SPPA$M_MASK_C 0x8 #define SPPA$M_MASK_D 0x10 #define SPPA$M_MASK_E 0x20 #define SPPA$M_MASK_F 0x40 #define SPPA$M_MASK_G 0x80 #define SPPA$M_RE 0x1 #define SPPA$M_ERR_CONFIG_CM 0x10 #define SPPA$M_ERR_CONFIG_S 0x20 #define SPPA$M_ERR_CONFIG_FS 0x40 #define SPPA$M_ERR_CONFIG_CT 0x400 #define SPPA$M_ERR_CONFIG_IM 0x800 #define SPPA$M_ERR_CONFIG_IT 0x1000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sppa_lba_map { #pragma __nomember_alignment SPPA_FUNC_HDR sppa$r_lba_hdr; char sppa$b_reserved_lba_1 [72]; __union { unsigned __int64 sppa$q_bus_number; /* 058 LBA Bus Number Range */ __struct { unsigned char sppa$b_lowest; /* Lowest bus number in LBA */ unsigned char sppa$b_highest; /* HIghest bus number in LBA */ char sppa$b_reserved_lba_2 [6]; } sppa$r_fill_27_; } sppa$r_fill_26_; char sppa$b_reserved_lba_3 [32]; __union { unsigned __int64 sppa$q_arb_mask; /* 080 Arbitration Mask */ __struct { __struct { /* Enables arbitration on PCI/X */ unsigned sppa$v_enable_arb : 1; /* Disable all requests if 0 */ unsigned sppa$v_mask_a : 1; /* Enable arbitration on device A */ unsigned sppa$v_mask_b : 1; /* Enable arbitration on device B */ unsigned sppa$v_mask_c : 1; /* Enable arbitration on device C */ unsigned sppa$v_mask_d : 1; /* Enable arbitration on device D */ unsigned sppa$v_mask_e : 1; /* Enable arbitration on device E */ unsigned sppa$v_mask_f : 1; /* Enable arbitration on device F */ unsigned sppa$v_mask_g : 1; /* Enable arbitration on device G */ } sppa$r_arb_mask_bits; } sppa$r_fill_29_; } sppa$r_fill_28_; char sppa$b_reserved_lba_4 [120]; /* */ SPPA_MOD_STATUS sppa$r_lba_mod; char sppa$b_reserved_lba_5 [496]; __union { unsigned __int64 sppa$q_ibase; /* 300 Base of IOV Space */ __struct { __struct { unsigned sppa$v_re : 1; /* Enable Mapping on Range */ unsigned sppa$v_fill_34_ : 7; } sppa$r_fill_ibase_bits; } sppa$r_fill_31_; } sppa$r_fill_30_; unsigned __int64 sppa$q_imask; /* 308 Mask/Size of IOV Space */ char sppa$b_reserved_lba_6 [880]; __union { unsigned __int64 sppa$q_err_config; /* 680 Define handling of various errors */ __struct { __struct { unsigned sppa$v_err_config_ip_1 : 4; /* Implementation dependent */ unsigned sppa$v_err_config_cm : 1; /* Config: master abort fatal if set */ unsigned sppa$v_err_config_s : 1; /* Smart bus if set */ unsigned sppa$v_err_config_fs : 1; /* SERR# fatal if set */ unsigned sppa$v_err_config_ip_2 : 3; /* Implementation dependent */ unsigned sppa$v_err_config_ct : 1; /* Config: target abort fatal if set */ unsigned sppa$v_err_config_im : 1; /* I/O port: master abort fatal if set */ unsigned sppa$v_err_config_it : 1; /* I/O port: target abort fatal if set */ unsigned sppa$v_err_config_ip_3 : 19; /* Implementation dependent */ unsigned sppa$v_reserved_lba_7 : 32; /* Reserved */ } sppa$r_fill_err_config; } sppa$r_fill_33_; } sppa$r_fill_32_; char sppa$b_reserved_lba_end [2424]; /* Pad to 4K */ } SPPA_LBA_MAP; #if !defined(__VAXC) #define sppa$q_bus_number sppa$r_fill_26_.sppa$q_bus_number #define sppa$b_lowest sppa$r_fill_26_.sppa$r_fill_27_.sppa$b_lowest #define sppa$b_highest sppa$r_fill_26_.sppa$r_fill_27_.sppa$b_highest #define sppa$q_arb_mask sppa$r_fill_28_.sppa$q_arb_mask #define sppa$v_enable_arb sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_enable_arb #define sppa$v_mask_a sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_a #define sppa$v_mask_b sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_b #define sppa$v_mask_c sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_c #define sppa$v_mask_d sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_d #define sppa$v_mask_e sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_e #define sppa$v_mask_f sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_f #define sppa$v_mask_g sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_g #define sppa$q_ibase sppa$r_fill_30_.sppa$q_ibase #define sppa$v_re sppa$r_fill_30_.sppa$r_fill_31_.sppa$r_fill_ibase_bits.sppa$v_re #define sppa$q_err_config sppa$r_fill_32_.sppa$q_err_config #define sppa$v_err_config_ip_1 sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_ip_1 #define sppa$v_err_config_cm sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_cm #define sppa$v_err_config_s sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_s #define sppa$v_err_config_fs sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_fs #define sppa$v_err_config_ip_2 sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_ip_2 #define sppa$v_err_config_ct sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_ct #define sppa$v_err_config_im sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_im #define sppa$v_err_config_it sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_it #define sppa$v_err_config_ip_3 sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_ip_3 #define sppa$v_reserved_lba_7 sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_reserved_lba_7 #endif /* #if !defined(__VAXC) */ #define SPPA$S_SPPA_LBA_MAP_LENGTH 4096 #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __SPPADEF_LOADED */