/***************************************************************************/ /** **/ /** HPE CONFIDENTIAL. This software is confidential proprietary software **/ /** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/ /** authorized to be used, duplicated OR disclosed to anyone without the **/ /** prior written permission of HPE. **/ /** © 2023 Copyright Hewlett-Packard Enterprise Development, LP **/ /** **/ /** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/ /** proprietary software licensed by VMS Software, Inc., and is not **/ /** authorized to be used, duplicated or disclosed to anyone without **/ /** the prior written permission of VMS Software, Inc. **/ /** © 2023 Copyright VMS Software, Inc. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 9-Nov-2023 12:06:45 by OpenVMS SDL V3.7 */ /* Source: 14-FEB-2008 15:31:23 $1$DGA8345:[LIB_H.SRC]IA64_SALDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $IA64_SALDEF ***/ #ifndef __IA64_SALDEF_LOADED #define __IA64_SALDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /*++ */ /* SAL Procedure Function IDs */ /* */ /* 0x01XXXXXX Architected SAL functional group. */ /* 0x02XXXXXX - 0x03XXXXXX OEM SAL functional group. */ /* 0x04XXXXXX - 0xFFFFFFFF Reserved. */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 9-2, Section 9.3, pp. 9-4 */ /*-- */ #define IA64_SAL$K_SET_VECTORS 16777216 #define IA64_SAL$K_GET_STATE_INFO 16777217 #define IA64_SAL$K_GET_STATE_INFO_SIZE 16777218 #define IA64_SAL$K_CLEAR_STATE_INFO 16777219 #define IA64_SAL$K_MC_RENDEZ 16777220 #define IA64_SAL$K_MC_SET_PARAMS 16777221 #define IA64_SAL$K_REG_PHYS_ADDR 16777222 #define IA64_SAL$K_CACHE_FLUSH 16777224 #define IA64_SAL$K_CACHE_INIT 16777225 #define IA64_SAL$K_PCI_CFG_READ 16777232 #define IA64_SAL$K_PCI_CFG_WRITE 16777233 #define IA64_SAL$K_FREQ_BASE 16777234 #define IA64_SAL$K_PHYSICAL_ID_INFO 16777235 #define IA64_SAL$K_UPDATE_PAL 16777248 /*++ */ /* SAL Procedure Generic Return Structure */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 8.2, pp. 8-5 */ /*-- */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_ret { #pragma __nomember_alignment __int64 sal_ret$q_status; unsigned __int64 sal_ret$q_ret1; unsigned __int64 sal_ret$q_ret2; unsigned __int64 sal_ret$q_ret3; } SAL_RET; #define SAL_RET$K_LENGTH 32 /*++ */ /* SAL Procedure Generic Return Status */ /* */ /* Each SAL procedure uses a subset of these return status values. */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 8-5, Section 8.2.2.1, pp. 8-7 */ /*-- */ #define IA64_SAL$K_MOREINFO 3 #define IA64_SAL$K_WARMBOOT 2 #define IA64_SAL$K_OVRFLW 1 #define IA64_SAL$K_SUCCESS 0 #define IA64_SAL$K_UNIMPL -1 #define IA64_SAL$K_INVALARG -2 #define IA64_SAL$K_FAIL -3 #define IA64_SAL$K_VANOTREG -4 #define IA64_SAL$K_NOINFO -5 #define IA64_SAL$K_BUFREQ -9 #define IA64_SAL$K_RETRY -15 /* SAL Procedures */ /*++ */ /* SAL_SET_VECTORS */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-21 */ /*-- */ /* Values for VEC_TYPE Argument */ #define SAL_SV$K_MCA 0 #define SAL_SV$K_INIT 1 #define SAL_SV$K_BOOT_RENDEZ 2 /* Structure for LEN_CS_N Argument */ #define SAL_SV$M_LEN_PROC 0xFFFFFFFF #define SAL_SV$M_CHECKSUM_PRES 0x100000000 #define SAL_SV$M_MOD_CHECKSUM 0xFF0000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sv_len_cs_n { #pragma __nomember_alignment __union { unsigned __int64 sal_sv$q_len_cs_n; __struct { unsigned sal_sv$v_len_proc : 32; unsigned sal_sv$v_checksum_pres : 1; unsigned sal_sv$v_reserved : 7; unsigned sal_sv$v_mod_checksum : 8; unsigned sal_sv$v_reserved_1 : 16; } sal_sv$r_len_cs_n_fields; } sal_sv$r_len_cs_n_overlay; } SAL_SV_LEN_CS_N; #if !defined(__VAXC) #define sal_sv$q_len_cs_n sal_sv$r_len_cs_n_overlay.sal_sv$q_len_cs_n #define sal_sv$v_len_proc sal_sv$r_len_cs_n_overlay.sal_sv$r_len_cs_n_fields.sal_sv$v_len_proc #define sal_sv$v_checksum_pres sal_sv$r_len_cs_n_overlay.sal_sv$r_len_cs_n_fields.sal_sv$v_checksum_pres #define sal_sv$v_mod_checksum sal_sv$r_len_cs_n_overlay.sal_sv$r_len_cs_n_fields.sal_sv$v_mod_checksum #endif /* #if !defined(__VAXC) */ #define SAL_SV_LEN_CS_N$K_LENGTH 8 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sv_ret { #pragma __nomember_alignment __int64 sal_sv_ret$q_status; unsigned __int64 sal_sv_ret$q_reserved; unsigned __int64 sal_sv_ret$q_reserved_1; unsigned __int64 sal_sv_ret$q_reserved_2; } SAL_SV_RET; #define SAL_SV_RET$K_LENGTH 32 /*++ */ /* SAL_GET_STATE_INFO */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-10 */ /*-- */ /* Values for TYPE Argument */ #define SAL_GSI$K_MCA 0 #define SAL_GSI$K_INIT 1 #define SAL_GSI$K_CMC 2 #define SAL_GSI$K_CPE 3 #define SAL_GSI$K_DECONFIGURED 4 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_gsi_ret { #pragma __nomember_alignment __int64 sal_gsi_ret$q_status; unsigned __int64 sal_gsi_ret$q_total_len; unsigned __int64 sal_gsi_ret$q_reserved; unsigned __int64 sal_gsi_ret$q_reserved_1; } SAL_GSI_RET; #define SAL_GSI_RET$K_LENGTH 32 /*++ */ /* SAL_GET_STATE_INFO_SIZE */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-12 */ /*-- */ /* Values for TYPE Argument */ #define SAL_GSIS$K_MCA 0 #define SAL_GSIS$K_INIT 1 #define SAL_GSIS$K_CMC 2 #define SAL_GSIS$K_CPE 3 #define SAL_GSIS$K_DECONFIGURED 4 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_gsis_ret { #pragma __nomember_alignment __int64 sal_gsis_ret$q_status; unsigned __int64 sal_gsis_ret$q_size; unsigned __int64 sal_gsis_ret$q_reserved; unsigned __int64 sal_gsis_ret$q_reserved_1; } SAL_GSIS_RET; #define SAL_GSIS_RET$K_LENGTH 32 /*++ */ /* SAL_CLEAR_STATE_INFO */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-8 */ /*-- */ /* Values for TYPE Argument */ #define SAL_CSI$K_MCA 0 #define SAL_CSI$K_INIT 1 #define SAL_CSI$K_CMC 2 #define SAL_CSI$K_CPE 3 #define SAL_CSI$K_DECONFIGURED 4 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_csi_ret { #pragma __nomember_alignment __int64 sal_csi_ret$q_status; unsigned __int64 sal_csi_ret$q_reserved; unsigned __int64 sal_csi_ret$q_reserved_1; unsigned __int64 sal_csi_ret$q_reserved_2; } SAL_CSI_RET; #define SAL_CSI_RET$K_LENGTH 32 /*++ */ /* SAL_MC_RENDEZ */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-13 */ /*-- */ /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_mcr_ret { #pragma __nomember_alignment __int64 sal_mcr_ret$q_status; unsigned __int64 sal_mcr_ret$q_reserved; unsigned __int64 sal_mcr_ret$q_reserved_1; unsigned __int64 sal_mcr_ret$q_reserved_2; } SAL_MCR_RET; #define SAL_MCR_RET$K_LENGTH 32 /*++ */ /* SAL_MC_SET_PARAMS */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-15 */ /*-- */ /* Values for PARAM_TYPE Argument */ #define SAL_MCSP$K_RENDEZ_INT 1 #define SAL_MCSP$K_WAKE_UP 2 #define SAL_MCSP$K_CPE_VEC 3 /* Values for I_OR_M Argument */ #define SAL_MCSP$K_INT_VEC 1 #define SAL_MCSP$K_MEM_ADDR 2 /* Structure for MCA_OPT Argument */ #define SAL_MCSP$M_RZ_ALWAYS 0x1 #define SAL_MCSP$M_BINIT_ESC 0x2 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_mcsp_mca_opt { #pragma __nomember_alignment __union { unsigned __int64 sal_mcsp$q_mca_opt; __struct { unsigned sal_mcsp$v_rz_always : 1; unsigned sal_mcsp$v_binit_esc : 1; unsigned sal_mcsp$v_reserved : 30; unsigned sal_mcsp$v_reserved_1 : 32; } sal_mcsp$r_mca_opt_fields; } sal_mcsp$r_mca_opt_overlay; } SAL_MCSP_MCA_OPT; #if !defined(__VAXC) #define sal_mcsp$q_mca_opt sal_mcsp$r_mca_opt_overlay.sal_mcsp$q_mca_opt #define sal_mcsp$v_rz_always sal_mcsp$r_mca_opt_overlay.sal_mcsp$r_mca_opt_fields.sal_mcsp$v_rz_always #define sal_mcsp$v_binit_esc sal_mcsp$r_mca_opt_overlay.sal_mcsp$r_mca_opt_fields.sal_mcsp$v_binit_esc #define sal_mcsp$v_reserved sal_mcsp$r_mca_opt_overlay.sal_mcsp$r_mca_opt_fields.sal_mcsp$v_reserved #define sal_mcsp$v_reserved_1 sal_mcsp$r_mca_opt_overlay.sal_mcsp$r_mca_opt_fields.sal_mcsp$v_reserved_1 #endif /* #if !defined(__VAXC) */ #define SAL_MCSP_MCA_OPT$K_LENGTH 8 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_mcsp_ret { #pragma __nomember_alignment __int64 sal_mcsp_ret$q_status; unsigned __int64 sal_mcsp_ret$q_time_out_min; unsigned __int64 sal_mcsp_ret$q_reserved; unsigned __int64 sal_mcsp_ret$q_reserved_1; } SAL_MCSP_RET; #define SAL_MCSP_RET$K_LENGTH 32 /*++ */ /* SAL_REG_PHYS_ADDR */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-20 */ /*-- */ /* Value for PHYS_ENTITY Argument */ #define SAL_RPA$K_PAL_PROC 0 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_rpa_ret { #pragma __nomember_alignment __int64 sal_rpa_ret$q_status; unsigned __int64 sal_rpa_ret$q_reserved; unsigned __int64 sal_rpa_ret$q_reserved_1; unsigned __int64 sal_rpa_ret$q_reserved_2; } SAL_RPA_RET; #define SAL_RPA_RET$K_LENGTH 32 /*++ */ /* SAL_CACHE_FLUSH */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-5 */ /*-- */ /* Values for I_OR_D Argument */ #define SAL_CF$K_FLUSH_ICACHE 1 #define SAL_CF$K_FLUSH_DCACHE 2 #define SAL_CF$K_FLUSH_BOTH 3 #define SAL_CF$K_MAKE_COHERENT 4 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_cf_ret { #pragma __nomember_alignment __int64 sal_cf_ret$q_status; unsigned __int64 sal_cf_ret$q_reserved; unsigned __int64 sal_cf_ret$q_reserved_1; unsigned __int64 sal_cf_ret$q_reserved_2; } SAL_CF_RET; #define SAL_CF_RET$K_LENGTH 32 /*++ */ /* SAL_CACHE_INIT */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-7 */ /*-- */ /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_ci_ret { #pragma __nomember_alignment __int64 sal_ci_ret$q_status; unsigned __int64 sal_ci_ret$q_reserved; unsigned __int64 sal_ci_ret$q_reserved_1; unsigned __int64 sal_ci_ret$q_reserved_2; } SAL_CI_RET; #define SAL_CI_RET$K_LENGTH 32 /*++ */ /* SAL_PCI_CFG_READ */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-18 */ /*-- */ /* Structure for ADDR Argument */ #define SAL_PCICR$M_REG_ADDR 0xFF #define SAL_PCICR$M_FUNC_NUM 0x700 #define SAL_PCICR$M_DEV_NUM 0xF800 #define SAL_PCICR$M_BUS_NUM 0xFF0000 #define SAL_PCICR$M_SEG_NUM 0xFF000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_pcicr_addr { #pragma __nomember_alignment __union { unsigned __int64 sal_pcicr$q_addr; __struct { unsigned sal_pcicr$v_reg_addr : 8; unsigned sal_pcicr$v_func_num : 3; unsigned sal_pcicr$v_dev_num : 5; unsigned sal_pcicr$v_bus_num : 8; unsigned sal_pcicr$v_seg_num : 8; unsigned sal_pcicr$v_reserved : 32; } sal_pcicr$r_addr_fields; } sal_pcicr$r_addr_overlay; } SAL_PCICR_ADDR; #if !defined(__VAXC) #define sal_pcicr$q_addr sal_pcicr$r_addr_overlay.sal_pcicr$q_addr #define sal_pcicr$v_reg_addr sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_reg_addr #define sal_pcicr$v_func_num sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_func_num #define sal_pcicr$v_dev_num sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_dev_num #define sal_pcicr$v_bus_num sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_bus_num #define sal_pcicr$v_seg_num sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_seg_num #endif /* #if !defined(__VAXC) */ #define SAL_PCICR_ADDR$K_LENGTH 8 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_pcicr_ret { #pragma __nomember_alignment __int64 sal_pcicr_ret$q_status; unsigned __int64 sal_pcicr_ret$q_value; unsigned __int64 sal_pcicr_ret$q_reserved; unsigned __int64 sal_pcicr_ret$q_reserved_1; } SAL_PCICR_RET; #define SAL_PCICR_RET$K_LENGTH 32 /*++ */ /* SAL_PCI_CFG_WRITE */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-19 */ /*-- */ /* Structure for ADDR Argument */ #define SAL_PCICW$M_REG_ADDR 0xFF #define SAL_PCICW$M_FUNC_NUM 0x700 #define SAL_PCICW$M_DEV_NUM 0xF800 #define SAL_PCICW$M_BUS_NUM 0xFF0000 #define SAL_PCICW$M_SEG_NUM 0xFF000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_pcicw_addr { #pragma __nomember_alignment __union { unsigned __int64 sal_pcicw$q_addr; __struct { unsigned sal_pcicw$v_reg_addr : 8; unsigned sal_pcicw$v_func_num : 3; unsigned sal_pcicw$v_dev_num : 5; unsigned sal_pcicw$v_bus_num : 8; unsigned sal_pcicw$v_seg_num : 8; unsigned sal_pcicw$v_reserved : 32; } sal_pcicw$r_addr_fields; } sal_pcicw$r_addr_overlay; } SAL_PCICW_ADDR; #if !defined(__VAXC) #define sal_pcicw$q_addr sal_pcicw$r_addr_overlay.sal_pcicw$q_addr #define sal_pcicw$v_reg_addr sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_reg_addr #define sal_pcicw$v_func_num sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_func_num #define sal_pcicw$v_dev_num sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_dev_num #define sal_pcicw$v_bus_num sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_bus_num #define sal_pcicw$v_seg_num sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_seg_num #endif /* #if !defined(__VAXC) */ #define SAL_PCICW_ADDR$K_LENGTH 8 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_pcicw_ret { #pragma __nomember_alignment __int64 sal_pcicw_ret$q_status; unsigned __int64 sal_pcicw_ret$q_reserved; unsigned __int64 sal_pcicw_ret$q_reserved_1; unsigned __int64 sal_pcicw_ret$q_reserved_2; } SAL_PCICW_RET; #define SAL_PCICW_RET$K_LENGTH 32 /*++ */ /* SAL_FREQ_BASE */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-9 */ /*-- */ /* Values for CLOCK_TYPE Argument */ #define SAL_FB$K_SYS_CLK_FREQ 0 #define SAL_FB$K_INT_TIMER 1 #define SAL_FB$K_REAL_TIME_CLK 2 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_fb_ret { #pragma __nomember_alignment __int64 sal_fb_ret$q_status; unsigned __int64 sal_fb_ret$q_reserved; unsigned __int64 sal_fb_ret$q_reserved_1; unsigned __int64 sal_fb_ret$q_reserved_2; } SAL_FB_RET; #define SAL_FB_RET$K_LENGTH 32 /* Return structure for PHYSICAL_ID_INFO */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_pid_ret { #pragma __nomember_alignment __int64 sal_pid_ret$q_status; unsigned short int sal_pid_ret$w_plid; unsigned short int sal_pid_ret$w_reserved_1; unsigned int sal_pid_ret$l_reserved_2; unsigned __int64 sal_pid_ret$q_reserved_3; unsigned __int64 sal_pid_ret$q_reserved_4; } SAL_PID_RET; #define SAL_PID_RET$K_LENGTH 32 /*++ */ /* SAL_UPDATE_PAL */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Section 9.3, pp. 9-21 */ /*-- */ /* Structure for PARAM_BUF Argument */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_upal_param_buf { #pragma __nomember_alignment unsigned __int64 sal_upal$q_next_ptr; unsigned __int64 sal_upal$q_upd_dat_blk_ptr; unsigned char sal_upal$b_checksum_flag; unsigned char sal_upal$b_reserved_1 [15]; } SAL_UPAL_PARAM_BUF; #define SAL_UPAL_PBUF$K_LENGTH 32 /* Structure for Update Data Block */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_upal_upd_dat_blk { #pragma __nomember_alignment unsigned int sal_upal$l_fw_size; unsigned int sal_upal$l_fw_date; unsigned short int sal_upal$w_fw_ver; unsigned char sal_upal$b_fw_type; unsigned char sal_upal$b_reserved [5]; unsigned __int64 sal_upal$q_fw_vend_id; unsigned char sal_upal$b_reserved_2 [40]; } SAL_UPAL_UPD_DAT_BLK; #define SAL_UPAL_UDBLK$K_LENGTH 64 /* Return Structure */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_upal_ret { #pragma __nomember_alignment __int64 sal_upal_ret$q_status; unsigned __int64 sal_upal_ret$q_error_code; unsigned __int64 sal_upal_ret$q_scrbuf_size_req; unsigned __int64 sal_upal_ret$q_reserved; } SAL_UPAL_RET; #define SAL_UPAL_RET$K_LENGTH 32 /* Value for ERROR_CODE Return Value */ #define SAL_UPAL$K_INCOMP_FW_VER -1 #define SAL_UPAL$K_AUTH_TEST_FAIL -2 #define SAL_UPAL$K_INV_FW_COMP -3 #define SAL_UPAL$K_FW_NOT_ERASE -4 #define SAL_UPAL$K_WRITE_FAIL -10 #define SAL_UPAL$K_ERASE_FAIL -11 #define SAL_UPAL$K_READ_FAIL -12 #define SAL_UPAL$K_INSUFF_SPACE -13 /* SAL System Table */ /*++ */ /* SAL System Table Header */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 3-2, Section 3.2.7, pp. 3-11 - 3-12 */ /*-- */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sys_tbl_hd { #pragma __nomember_alignment unsigned char sal_sthd$b_sig [4]; unsigned int sal_sthd$l_total_tbl_len; __union { unsigned short int sal_sthd$w_sal_rev; __struct { unsigned char sal_sthd$b_minor_sal_rev; unsigned char sal_sthd$b_major_sal_rev; } sal_sthd$r_sal_rev_fields; } sal_sthd$r_sal_rev_overlay; unsigned short int sal_sthd$w_entry_count; unsigned char sal_sthd$b_checksum; unsigned char sal_sthd$b_reserved [7]; __union { unsigned short int sal_sthd$w_sal_a_ver; __struct { unsigned char sal_sthd$b_minor_sal_a_ver; unsigned char sal_sthd$b_major_sal_a_ver; } sal_sthd$r_sal_a_ver_fields; } sal_sthd$r_sal_a_ver_overlay; __union { unsigned short int sal_sthd$w_sal_b_ver; __struct { unsigned char sal_sthd$b_minor_sal_b_ver; unsigned char sal_sthd$b_major_sal_b_ver; } sal_sthd$r_sal_b_ver_fields; } sal_sthd$r_sal_b_ver_overlay; unsigned char sal_sthd$b_oem_id [32]; unsigned char sal_sthd$b_product_id [32]; unsigned char sal_sthd$b_reserved_1 [8]; } SAL_SYS_TBL_HD; #if !defined(__VAXC) #define sal_sthd$w_sal_rev sal_sthd$r_sal_rev_overlay.sal_sthd$w_sal_rev #define sal_sthd$b_minor_sal_rev sal_sthd$r_sal_rev_overlay.sal_sthd$r_sal_rev_fields.sal_sthd$b_minor_sal_rev #define sal_sthd$b_major_sal_rev sal_sthd$r_sal_rev_overlay.sal_sthd$r_sal_rev_fields.sal_sthd$b_major_sal_rev #define sal_sthd$w_sal_a_ver sal_sthd$r_sal_a_ver_overlay.sal_sthd$w_sal_a_ver #define sal_sthd$b_minor_sal_a_ver sal_sthd$r_sal_a_ver_overlay.sal_sthd$r_sal_a_ver_fields.sal_sthd$b_minor_sal_a_ver #define sal_sthd$b_major_sal_a_ver sal_sthd$r_sal_a_ver_overlay.sal_sthd$r_sal_a_ver_fields.sal_sthd$b_major_sal_a_ver #define sal_sthd$w_sal_b_ver sal_sthd$r_sal_b_ver_overlay.sal_sthd$w_sal_b_ver #define sal_sthd$b_minor_sal_b_ver sal_sthd$r_sal_b_ver_overlay.sal_sthd$r_sal_b_ver_fields.sal_sthd$b_minor_sal_b_ver #define sal_sthd$b_major_sal_b_ver sal_sthd$r_sal_b_ver_overlay.sal_sthd$r_sal_b_ver_fields.sal_sthd$b_major_sal_b_ver #endif /* #if !defined(__VAXC) */ #define SAL_STHD$K_LENGTH 96 /*++ */ /* SAL System Table Entrypoint Descriptor Entry */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 3-4, Section 3.2.7.1, pp. 3-12 */ /*-- */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sys_tbl_epd { #pragma __nomember_alignment unsigned char sal_stepd$b_entry_type; unsigned char sal_stepd$b_reserved [7]; unsigned __int64 sal_stepd$q_phys_addr_pal_proc; unsigned __int64 sal_stepd$q_phys_addr_sal_proc; unsigned __int64 sal_stepd$q_gp_sal; unsigned int sal_stepd$o_reserved_1 [4]; } SAL_SYS_TBL_EPD; #define SAL_STEPD$K_LENGTH 48 /*++ */ /* SAL System Table Memory Descriptor Entry */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 3-5, Section 3.2.7.2, pp. 3-13 - 3-14 */ /*-- */ #define SAL_STMD$M_NEED_VA_REG 0x1 #define SAL_STMD$M_MEM_ATTR_SET 0x7 #define SAL_STMD$M_WB 0x1 #define SAL_STMD$M_UC 0x2 #define SAL_STMD$M_UCE 0x4 #define SAL_STMD$M_WC 0x8 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sys_tbl_md { #pragma __nomember_alignment unsigned char sal_stmd$b_entry_type; __union { unsigned char sal_stmd$b_need_va_reg; __struct { unsigned sal_stmd$v_need_va_reg : 1; unsigned sal_stmd$v_reserved : 7; } sal_stmd$r_need_va_reg_fields; } sal_stmd$r_need_va_reg_overlay; __union { unsigned char sal_stmd$b_mem_attr_set; __struct { unsigned sal_stmd$v_mem_attr_set : 3; unsigned sal_stmd$v_reserved_1 : 5; } sal_stmd$r_mem_attr_set_fields; } sal_stmd$r_mem_attr_set_overlay; unsigned char sal_stmd$b_page_access_rights; __union { unsigned char sal_stmd$b_mem_attr_sup; __struct { unsigned sal_stmd$v_wb : 1; unsigned sal_stmd$v_uc : 1; unsigned sal_stmd$v_uce : 1; unsigned sal_stmd$v_wc : 1; unsigned sal_stmd$v_reserved : 4; } sal_stmd$r_mem_attr_sup_fields; } sal_stmd$r_mem_attr_sup_overlay; unsigned char sal_stmd$b_reserved_2; unsigned char sal_stmd$b_mem_type; unsigned char sal_stmd$b_mem_usage; unsigned __int64 sal_stmd$q_phys_addr; unsigned int sal_stmd$l_num_4k_pages; unsigned int sal_stmd$l_reserved_3; unsigned __int64 sal_stmd$q_oem_reserved; } SAL_SYS_TBL_MD; #if !defined(__VAXC) #define sal_stmd$b_need_va_reg sal_stmd$r_need_va_reg_overlay.sal_stmd$b_need_va_reg #define sal_stmd$v_need_va_reg sal_stmd$r_need_va_reg_overlay.sal_stmd$r_need_va_reg_fields.sal_stmd$v_need_va_reg #define sal_stmd$b_mem_attr_set sal_stmd$r_mem_attr_set_overlay.sal_stmd$b_mem_attr_set #define sal_stmd$v_mem_attr_set sal_stmd$r_mem_attr_set_overlay.sal_stmd$r_mem_attr_set_fields.sal_stmd$v_mem_attr_set #define sal_stmd$b_mem_attr_sup sal_stmd$r_mem_attr_sup_overlay.sal_stmd$b_mem_attr_sup #define sal_stmd$v_wb sal_stmd$r_mem_attr_sup_overlay.sal_stmd$r_mem_attr_sup_fields.sal_stmd$v_wb #define sal_stmd$v_uc sal_stmd$r_mem_attr_sup_overlay.sal_stmd$r_mem_attr_sup_fields.sal_stmd$v_uc #define sal_stmd$v_uce sal_stmd$r_mem_attr_sup_overlay.sal_stmd$r_mem_attr_sup_fields.sal_stmd$v_uce #define sal_stmd$v_wc sal_stmd$r_mem_attr_sup_overlay.sal_stmd$r_mem_attr_sup_fields.sal_stmd$v_wc #endif /* #if !defined(__VAXC) */ #define SAL_STMD$K_LENGTH 32 /*++ */ /* SAL System Table Platform Features Descriptor Entry */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 3-7, Section 3.2.7.3, pp. 3-15 - 3-16 */ /*-- */ #define SAL_STSFD$M_BUS_LOCK 0x1 #define SAL_STSFD$M_SYS_INT_REDIR 0x2 #define SAL_STSFD$M_PROC_IPI_MSG_REDIR 0x4 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sys_tbl_sfd { #pragma __nomember_alignment unsigned char sal_stsfd$b_entry_type; __union { unsigned char sal_stsfd$b_sys_feat; __struct { unsigned sal_stsfd$v_bus_lock : 1; unsigned sal_stsfd$v_sys_int_redir : 1; unsigned sal_stsfd$v_proc_ipi_msg_redir : 1; unsigned sal_stsfd$v_reserved : 5; } sal_stsfd$r_sys_feat_fields; } sal_stsfd$r_sys_feat_overlay; unsigned char sal_stsfd$b_reserved_1 [14]; } SAL_SYS_TBL_SFD; #if !defined(__VAXC) #define sal_stsfd$b_sys_feat sal_stsfd$r_sys_feat_overlay.sal_stsfd$b_sys_feat #define sal_stsfd$v_bus_lock sal_stsfd$r_sys_feat_overlay.sal_stsfd$r_sys_feat_fields.sal_stsfd$v_bus_lock #define sal_stsfd$v_sys_int_redir sal_stsfd$r_sys_feat_overlay.sal_stsfd$r_sys_feat_fields.sal_stsfd$v_sys_int_redir #define sal_stsfd$v_proc_ipi_msg_redir sal_stsfd$r_sys_feat_overlay.sal_stsfd$r_sys_feat_fields.sal_stsfd$v_proc_ipi_msg_redir #endif /* #if !defined(__VAXC) */ #define SAL_STSFD$K_LENGTH 16 /*++ */ /* SAL System Table Translation Register Descriptor Entry */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 3-8, Section 3.2.7.4, pp. 3-16 */ /*-- */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sys_tbl_trd { #pragma __nomember_alignment unsigned char sal_sttrd$b_entry_type; unsigned char sal_sttrd$b_trans_reg_type; unsigned char sal_sttrd$b_trans_reg_num; unsigned char sal_sttrd$b_reserved [5]; unsigned __int64 sal_sttrd$q_va_trans_reg; unsigned __int64 sal_sttrd$q_page_size_trans_reg; unsigned __int64 sal_sttrd$q_reserved_1; } SAL_SYS_TBL_TRD; #define SAL_STRDD$K_LENGTH 32 /*++ */ /* SAL System Table Purge Translation Cache Coherence Domain Entry */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 3-9, Section 3.2.7.5, pp. 3-16 */ /*-- */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sys_tbl_ptccd { #pragma __nomember_alignment unsigned char sal_stptccd$b_entry_type; unsigned char sal_stptccd$b_reserved [3]; unsigned int sal_stptccd$l_num_sys_coh_dom; unsigned __int64 sal_stptccd$q_coh_dom_data_addr; } SAL_SYS_TBL_PTCCD; #define SAL_STPTCCD$K_LENGTH 16 /*++ */ /* SAL System Table Application Processor Wake-up Descriptor Entry */ /* */ /* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */ /* Table 3-11, Section 3.2.7.6, pp. 3-17 */ /*-- */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _sal_sys_tbl_apwud { #pragma __nomember_alignment unsigned char sal_stapwud$b_entry_type; unsigned char sal_stapwud$b_wake_up_mech_type; unsigned char sal_stapwud$b_reserved [6]; unsigned __int64 sal_stapwud$q_ex_intvec_10_ff; } SAL_SYS_TBL_APWUD; #define SAL_STAPWUD$K_LENGTH 16 #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __IA64_SALDEF_LOADED */