/***************************************************************************/ /** **/ /** HPE CONFIDENTIAL. This software is confidential proprietary software **/ /** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/ /** authorized to be used, duplicated OR disclosed to anyone without the **/ /** prior written permission of HPE. **/ /** © 2023 Copyright Hewlett-Packard Enterprise Development, LP **/ /** **/ /** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/ /** proprietary software licensed by VMS Software, Inc., and is not **/ /** authorized to be used, duplicated or disclosed to anyone without **/ /** the prior written permission of VMS Software, Inc. **/ /** © 2023 Copyright VMS Software, Inc. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 9-Nov-2023 12:06:44 by OpenVMS SDL V3.7 */ /* Source: 03-JAN-2023 14:11:28 $1$DGA8345:[LIB_H.SRC]HWRPBDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $HWRPBDEF ***/ #ifndef __HWRPBDEF_LOADED #define __HWRPBDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif #ifdef EFI64 #pragma pack(push,hwrpbdef) #pragma pack(8) #pragma warning(disable:4068) #endif /********** X86_64 SECTION ************************************************ */ /* Verified for X86_64 port - GM Newsted */ /********** CONSTANTS ***************************************************** */ #define HWRPB_BOOT_FLAGS$M_SYSPROMPT 0x1 #define HWRPB_BOOT_FLAGS$M_XDELTA 0x2 #define HWRPB_BOOT_FLAGS$M_BREAKPOINT 0x4 #define HWRPB_BOOT_FLAGS$M_DK_SDA 0x8 #define HWRPB_BOOT_FLAGS$M_PROGRESS 0x10 #define HWRPB_BOOT_FLAGS$M_SYSBOOT 0x20 #define HWRPB_BOOT_FLAGS$M_EXECINIT 0x40 #define HWRPB_BOOT_FLAGS$M_SYSINIT 0x80 #define HWRPB_BOOT_FLAGS$M_DRIVER 0x100 #define HWRPB_BOOT_FLAGS$M_SHADOW 0x200 #define HWRPB_BOOT_FLAGS$M_NETBOOT 0x400 #define HWRPB_BOOT_FLAGS$M_SYSDEBUG 0x800 #define HWRPB_BOOT_FLAGS$M_ACPI 0x1000 #define HWRPB_BOOT_FLAGS$M_HW_CONFIG 0x2000 #define HWRPB_BOOT_FLAGS$M_PAGE_FAULTS 0x4000 #define HWRPB_BOOT_FLAGS$M_HALT 0x8000 #define HWRPB_BOOT_FLAGS$M_DK_NOSYSD 0x10000 #define HWRPB_BOOT_FLAGS$M_X20000 0x20000 #define HWRPB_BOOT_FLAGS$M_X40000 0x40000 #define HWRPB_BOOT_FLAGS$M_X80000 0x80000 #define HWRPB_BOOT_FLAGS$M_X100000 0x100000 #define HWRPB_BOOT_FLAGS$M_X200000 0x200000 #define HWRPB_BOOT_FLAGS$M_X400000 0x400000 #define HWRPB_BOOT_FLAGS$M_OPDISPLAY 0x800000 #define HWRPB_BOOT_FLAGS$M_BOOTMGR 0x1000000 #define HWRPB_BOOT_FLAGS$M_MEMCHECK 0x2000000 #define HWRPB_BOOT_FLAGS$M_DEVCHECK 0x4000000 #define HWRPB_BOOT_FLAGS$M_DEVELOPER 0x8000000 #define HWRPB_BOOT_FLAGS$M_MDCHECK 0x10000000 #define HWRPB_BOOT_FLAGS$M_CPUCHECK 0x20000000 #define HWRPB_BOOT_FLAGS$M_X40000000 0x40000000 #define HWRPB_BOOT_FLAGS$M_VERBOSE 0x80000000 #define HWRPB_BOOT_FLAGS$M_ROOT 0xFFFF0000 #define HWRPB_SYSTYPE$K_GENERIC 64 #define HWRPB_SYSTYPE$K_X86_GENERIC 128 #define HWRPB_SYSTYPE$K_X86_INTEL 129 #define HWRPB_SYSTYPE$K_X86_AMD 130 #define HWRPB_SYSTYPE$K_MAX_SYSTYPE 130 #define HWRPB_SYSVAR$M_MPCAP 0x1 #define HWRPB_SYSVAR$M_CNSLE 0x1E #define HWRPB_SYSVAR$M_KEYBOARD 0xE0 #define HWRPB_SYSVAR$M_DUMPBOOT 0x100 #define HWRPB_SYSVAR$M_GRAPHICS 0x200 #define HWRPB_SYSVAR$M_MEMBER_ID 0xFC00 #define HWRPB_SYSVAR$M_FILL1 0x1 #define HWRPB_SYSVAR$M_RXTX_EXTENT 0x2 #define HWRPB_KEYBOARD$K_NONE 0 #define HWRPB_KEYBOARD$K_PS2 1 #define HWRPB_KEYBOARD$K_USB 2 #define HWRPB_VM_TYPE$K_NONE 0 #define HWRPB_VM_TYPE$K_VMWARE 1 #define HWRPB_VM_TYPE$K_KVM 2 #define HWRPB_VM_TYPE$K_VIRTUALBOX 3 #define HWRPB_VM_TYPE$K_XEN 4 #define HWRPB_VM_TYPE$K_HYPER_V 5 #define HWRPB_MEMBER_ID$K_INTEL 1 #define HWRPB_MEMBER_ID$K_AMD 2 /************************************************************************** */ #define HWRPB_TXRDY$M_TXRDY_SUMMARY 0x1 #define HWRPB_BOOTDEV$M_FUNCT 0x7 #define HWRPB_BOOTDEV$M_DEVICE 0xF8 #define HWRPB_BOOTDEV$M_BUS 0xFF00 #define HWRPB_BOOTDEV$M_HOSE 0xFF0000 #define HWRPB_BOOTDEV$M_PCINODE_FILL1 0xFF000000 #define HWRPB_ALTDEV$M_FUNCT 0x7 #define HWRPB_ALTDEV$M_DEVICE 0xF8 #define HWRPB_ALTDEV$M_BUS 0xFF00 #define HWRPB_ALTDEV$M_HOSE 0xFF0000 #define HWRPB_ALTDEV$M_ALTNODE_FILL1 0xFF000000 #define HWRPB_UART_PCICFG$M_FUNCTION 0x7 #define HWRPB_UART_PCICFG$M_DEVICE 0xF8 #define HWRPB_UART_PCICFG$M_BUS 0xFF00 #define HWRPB_UART_PCICFG$M_OFFSET 0xFFFF0000 #define HWRPB_VGA_PCICFG$M_FUNCTION 0x7 #define HWRPB_VGA_PCICFG$M_DEVICE 0xF8 #define HWRPB_VGA_PCICFG$M_BUS 0xFF00 #define HWRPB_VGA_PCICFG$M_OFFSET 0xFFFF0000 #define HWRPB_VGA_FLAG$M_CONSOLE 0x1 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __octaword #else #pragma __nomember_alignment #endif typedef struct _hwrpb { /************************************************************************** */ /* [X86-64] HWRPB-Related Items */ /************************************************************************** */ #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwrpb$pq_base; /* Booted HWRPB PA */ #else unsigned __int64 hwrpb$pq_base; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwrpb$pq_vbase; /* Booted HWRPB VA */ #else unsigned __int64 hwrpb$pq_vbase; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwrpb$pq_alt_hwrpb; /* Alt kernel HWRPB */ #else unsigned __int64 hwrpb$pq_alt_hwrpb; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwrpb$pq_swrpb; /* Ptr to SWRPB */ #else unsigned __int64 hwrpb$pq_swrpb; #endif unsigned __int64 hwrpb$iq_size; /* Size of HWRPB */ unsigned __int64 hwrpb$iq_ident; /* Sig "X86_RPB\0" */ unsigned __int64 hwrpb$iq_revision; /* 1 for VMS9.1 X86_64 */ /************************************************************************** */ /* [X86-64] MACHINE DETAILS */ /************************************************************************** */ unsigned __int64 hwrpb$iq_primary; /* Primary CPU ID/Slot */ unsigned __int64 hwrpb$iq_nproc; /* Number of Per-CPU slots */ unsigned __int64 hwrpb$iq_clock_int_freq; /* Clock intr freq */ unsigned __int64 hwrpb$iq_itc_freq; /* TSC update intr freq */ unsigned __int64 hwrpb$iq_cycle_count_freq; /* Cycle Counter freq */ unsigned __int64 hwrpb$iq_com_port_number; /* Selected COM Port */ unsigned __int64 hwrpb$iq_com_port_reg; /* Selected COM Port Reg */ unsigned int hwrpb$il_horiz_rez; /* Display Width or zero */ unsigned int hwrpb$il_vert_rez; /* Display Height or zero */ /************************************************************************** */ /* [X86-64] ADDRESSES AND APPLICABLE SIZES */ /************************************************************************** */ unsigned __int64 hwrpb$iq_framebuffer_pa; /* PA of Framebuffer or NULL */ unsigned __int64 hwrpb$iq_framebuffer_size; /* Size of Framebuffer or zero */ unsigned __int64 hwrpb$iq_conio_base_pa; /* PA of Console Service Table */ unsigned __int64 hwrpb$iq_st_base_pa; /* PA of UEFI Service Table */ unsigned __int64 hwrpb$iq_sysboot_pa; /* PA of SYSBOOT */ unsigned __int64 hwrpb$iq_sysboot_size; /* Size of SYSBOOT */ unsigned __int64 hwrpb$iq_memdisk_pa; /* PA of MEMDISK */ unsigned __int64 hwrpb$iq_memdisk_size; /* Size of MEMDISK */ unsigned __int64 hwrpb$iq_mmap_pa; /* PA of UEFI Memory Map */ unsigned __int64 hwrpb$iq_mmap_size; /* Size of Memory Map */ unsigned __int64 hwrpb$iq_mmap_entry_size; /* Size of Memory Map Entry */ unsigned __int64 hwrpb$iq_mmap_key; /* Memory Map Key */ unsigned int hwrpb$il_mmap_version; /* Memory Map Version */ unsigned int hwrpb$il_mmap_rsvd; /* For alignment */ unsigned __int64 hwrpb$iq_acpi_rsdp_pa; /* PA of ACPI RSDP Table */ unsigned __int64 hwrpb$iq_restart; /* VA of Restart Routine */ unsigned __int64 hwrpb$iq_dump_transfer_pa; /* PA of Dump Kernel Transfer */ unsigned __int64 hwrpb$iq_hpet_base_pa; /* PA of Clock Registers */ /************************************************************************** */ /* [X86-64] BOOT FLAGS & BOOT RELATED ITEMS */ /************************************************************************** */ __union { unsigned __int64 hwrpb$iq_boot_flags; __struct { __union { unsigned int hwrpb$il_boot_flags_l; __struct { unsigned hwrpb_boot_flags$v_sysprompt : 1; /* <0>0 SYSBOOT> Conversation */ unsigned hwrpb_boot_flags$v_xdelta : 1; /* <1>2 Load XDELTA execlet */ unsigned hwrpb_boot_flags$v_breakpoint : 1; /* <2>4 Breakpoint in X(L)DELTA */ unsigned hwrpb_boot_flags$v_dk_sda : 1; /* <3>8 Dump Kernel only: activate SDA */ unsigned hwrpb_boot_flags$v_progress : 1; /* <4>10 Boot Progress Messages */ unsigned hwrpb_boot_flags$v_sysboot : 1; /* <5>20 SYSBOOT Messages */ unsigned hwrpb_boot_flags$v_execinit : 1; /* <6>40 EXECINIT Messages */ unsigned hwrpb_boot_flags$v_sysinit : 1; /* <7>80 SYSINIT Messages */ unsigned hwrpb_boot_flags$v_driver : 1; /* <8>100 DRIVER Messages */ unsigned hwrpb_boot_flags$v_shadow : 1; /* <9>200 Boot from shadow set */ unsigned hwrpb_boot_flags$v_netboot : 1; /* <10>400 Boot from network device */ unsigned hwrpb_boot_flags$v_sysdebug : 1; /* <11>800 Load the System Code Debugger */ unsigned hwrpb_boot_flags$v_acpi : 1; /* <12>1000 ACPI Config Messages */ unsigned hwrpb_boot_flags$v_hw_config : 1; /* <13>2000 HW Config Messages */ unsigned hwrpb_boot_flags$v_page_faults : 1; /* <14>4000 issue TR_PRINTs for page faults */ unsigned hwrpb_boot_flags$v_halt : 1; /* <15>8000 Halt before transfer to SYSBOOT */ unsigned hwrpb_boot_flags$v_dk_nosysd : 1; /* <16>10000 Dump Kernel only: avoid System Disk */ unsigned hwrpb_boot_flags$v_x20000 : 1; /* <17>20000 Spare */ unsigned hwrpb_boot_flags$v_x40000 : 1; /* <18>40000 Spare */ unsigned hwrpb_boot_flags$v_x80000 : 1; /* <19>80000 Spare */ unsigned hwrpb_boot_flags$v_x100000 : 1; /* <20>100000 Spare */ unsigned hwrpb_boot_flags$v_x200000 : 1; /* <21>200000 Spare */ unsigned hwrpb_boot_flags$v_x400000 : 1; /* <22>400000 Spare */ unsigned hwrpb_boot_flags$v_opdisplay : 1; /* <23>800000 Display OPA0 messages after boot */ unsigned hwrpb_boot_flags$v_bootmgr : 1; /* <24>1000000 BOOTMGR> Conversation */ unsigned hwrpb_boot_flags$v_memcheck : 1; /* <25>2000000 BootMgr Memory Info */ unsigned hwrpb_boot_flags$v_devcheck : 1; /* <26>4000000 BootMgr Device Info */ unsigned hwrpb_boot_flags$v_developer : 1; /* <27>8000000 Developer Functions */ unsigned hwrpb_boot_flags$v_mdcheck : 1; /* <28>10000000 MemoryDisk Diagnostic */ unsigned hwrpb_boot_flags$v_cpucheck : 1; /* <29>20000000 CPU Init Diagnostic */ unsigned hwrpb_boot_flags$v_x40000000 : 1; /* <30>40000000 Spare */ unsigned hwrpb_boot_flags$v_verbose : 1; /* <31>80000000 Verbose Messages */ } hwrpb$r_boot_flags_field_l; } hwrpb$r_boot_flags_overlay_l; __union { unsigned int hwrpb$il_boot_flags_h; __struct { unsigned hwrpb_boot_flags$v_boot_flags_fill : 16; unsigned hwrpb_boot_flags$v_root : 16; /* System Root */ } hwrpb$r_boot_flags_field_h; } hwrpb$r_boot_flags_overlay_h; } hwrpb$r_boot_flags_fields; } hwrpb$r_boot_flags_overlay; __union { /* USB Boot Device */ unsigned __int64 hwrpb$iq_usb_flags; __struct { unsigned short int hwrpb_usb$w_vendor_id; unsigned short int hwrpb_usb$w_product_id; unsigned char hwrpb_usb$b_interface_class; unsigned char hwrpb_usb$b_interface_subclass; unsigned char hwrpb_usb$b_interface_protocol; unsigned char hwrpb_usb$b_serialnum_len; } hwrpb$r_usb_bits; } hwrpb$r_usb_bootdev_overlay; unsigned char hwrpb$b_usb_serialnum [256]; char hwrpb$t_device_name [32]; /* Network BootDev Name */ unsigned char hwrpb$b_service_name [256]; /* Network Boot Service */ /************************************************************************** */ /* [X86-64] SYSTEM IDENTIFICATION */ /************************************************************************** */ unsigned __int64 hwrpb$iq_system_revision; /* System Rev */ unsigned char hwrpb$b_sys_phys_serialnum [16]; /* Physical S/N */ unsigned char hwrpb$b_sys_serialnum [16]; /* Virtual S/N */ unsigned __int64 hwrpb$iq_systype; /* System Type */ __union { /* System Variation */ unsigned __int64 hwrpb$iq_sysvar; __struct { __union { unsigned int hwrpb$il_sysvar_l; __struct { unsigned hwrpb_sysvar$v_mpcap : 1; /* Capable of SMP */ unsigned hwrpb_sysvar$v_cnsle : 4; /* Console Type */ unsigned hwrpb_sysvar$v_keyboard : 3; /* Boot Keyboard Type */ unsigned hwrpb_sysvar$v_dumpboot : 1; /* Dump Kernel booted */ unsigned hwrpb_sysvar$v_graphics : 1; /* Embedded graphics */ unsigned hwrpb_sysvar$v_member_id : 6; /* Member ID field */ signed hwrpb_sysvar$ib_vm_type : 8; /* Virtual Machine Host Type */ signed hwrpb_sysvar$ib_vm_config : 8; /* Virtual Machine Config */ } hwrpb$r_sysvar_field1; } hwrpb$r_sysvar_fields_overlay; __union { unsigned int hwrpb$il_sysvar_h; __struct { unsigned hwrpb_sysvar$v_fill1 : 1; unsigned hwrpb_sysvar$v_rxtx_extent : 1; /* ECO-123 >64 CPU enable */ unsigned hwrpb_sysvar$v_fill2 : 30; } hwrpb$r_sysvar_field3; } hwrpb$r_sysvar_h_fields_overlay; } hwrpb$r_sysvar_fields; } hwrpb$r_sysvar_overlay; /* [X86-64] OFFSET & SIZES FOR MAJOR BOOT STRUCTURES */ /************************************************************************** */ __int64 hwrpb$iq_kernel_base_offset; /* External Negative */ unsigned __int64 hwrpb$iq_kernel_base_size; __int64 hwrpb$iq_whami_offset; /* External Negative */ unsigned __int64 hwrpb$iq_whami_size; unsigned __int64 hwrpb$iq_mcd_list_offset; /* Internal */ unsigned __int64 hwrpb$iq_mcd_entry_size; unsigned __int64 hwrpb$iq_conindev_offset; /* Internal */ unsigned __int64 hwrpb$iq_conindev_size; unsigned __int64 hwrpb$iq_conoutdev_offset; /* Internal */ unsigned __int64 hwrpb$iq_conoutdev_size; unsigned __int64 hwrpb$iq_conerrdev_offset; /* Internal */ unsigned __int64 hwrpb$iq_conerrdev_size; unsigned __int64 hwrpb$iq_bootdev_offset; /* Internal */ unsigned __int64 hwrpb$iq_bootdev_size; unsigned __int64 hwrpb$iq_altdev_offset; /* Internal */ unsigned __int64 hwrpb$iq_altdev_size; unsigned __int64 hwrpb$iq_slot_offset; /* Internal */ unsigned __int64 hwrpb$iq_slot_entry_size; unsigned __int64 hwrpb$iq_swis_offset; /* Internal */ unsigned __int64 hwrpb$iq_swis_entry_size; unsigned __int64 hwrpb$iq_crb_offset; /* Internal */ unsigned __int64 hwrpb$iq_crb_size; unsigned __int64 hwrpb$iq_cmd_buf_offset; /* Internal */ unsigned __int64 hwrpb$iq_cmd_buf_size; /* */ /* ECO-123 pertains to support of >64 processors. When enabled, the */ /* RXRDY_OFFSET field points to a CBB (Common Bit Block) structure */ /* containing bits for additional processors. Each of the traditional */ /* 64 CPU_ID bits then indexes quadword bitmasks within the CBB, each */ /* representing another 64 processors. */ /* */ __union { /* Internal */ unsigned __int64 hwrpb$iq_rxrdy; /* Intercom RXRDY bitmask */ unsigned __int64 hwrpb$iq_rxrdy_offset; /* CBB bitmask offset */ } hwrpb$r_rxrdy_overlay; __union { /* Internal */ unsigned __int64 hwrpb$iq_txrdy; /* Intercom TXRDY bitmask */ __struct { __union { unsigned int hwrpb$il_txrdy_l; __struct { unsigned hwrpb_txrdy$v_txrdy_summary : 1; /* CBB - At least 1 bitmask is nonzero */ unsigned hwrpb_txrdy$v_txrdy_fill1 : 31; } hwrpb$r_txrdy_field1; } hwrpb$r_txrdy_fields_overlay; unsigned int hwrpb$il_txrdy_h; } hwrpb$r_txrdy_fields; } hwrpb$r_txrdy_overlay; /************************************************************************** */ /* [X86-64] OFFSET BOOT STRUCTURES (Internal to HWRPB memory allocation) */ /************************************************************************** */ __union { /* BOOT DEVICE */ unsigned __int64 hwrpb$iq_bootdev_pcinode; __struct { __union { unsigned int hwrpb$il_bootdev_pcinode_l; __struct { unsigned hwrpb_bootdev$v_funct : 3; unsigned hwrpb_bootdev$v_device : 5; unsigned hwrpb_bootdev$v_bus : 8; unsigned hwrpb_bootdev$v_hose : 8; unsigned hwrpb_bootdev$v_pcinode_fill1 : 8; } hwrpb$r_bootdev_pcinode_l_fields; } hwrpb$r_bootdev_pcinode_l_overlay; __union { unsigned int hwrpb$il_bootdev_pcinode_h; unsigned int hwrpb$il_sysdisk_unit; } hwrpb$r_bootdev_pcinode_h_overlay; } hwrpb$r_bootdev_pcinode_fields; } hwrpb$r_bootdev_pcinode_overlay; __union { /* ALTERNATE BOOT DEVICE */ unsigned __int64 hwrpb$iq_altdev_pcinode; __struct { __union { unsigned int hwrpb$il_altdev_pcinode_l; __struct { unsigned hwrpb_altdev$v_funct : 3; unsigned hwrpb_altdev$v_device : 5; unsigned hwrpb_altdev$v_bus : 8; unsigned hwrpb_altdev$v_hose : 8; unsigned hwrpb_altdev$v_altnode_fill1 : 8; } hwrpb$r_altdev_pcinode_l_fields; } hwrpb$r_altdev_pcinode_l_overlay; unsigned int hwrpb$il_altdev_pcinode_h; } hwrpb$r_altdev_pcinode_fields; } hwrpb$r_altdev_pcinode_overlay; /************************************************************************** */ /* [X86-64] CONSOLE & MCA ERROR BUFFERS (NOT YET USED ON X86) */ /************************************************************************** */ unsigned __int64 hwrpb$iq_cdl_pa; /* PA Console Data Log */ __union { unsigned __int64 hwrpb$iq_cdl_size_count; __struct { unsigned int hwrpb$il_cdl_size; unsigned int hwrpb$il_cdl_count; } hwrpb$r_cdl_size_count_fields; } hwrpb$r_cdl_size_count_overlay; unsigned __int64 hwrpb$iq_mca_error_record; /* PA MCA err rec buffer */ __union { unsigned __int64 hwrpb$iq_mca_record_size_count; __struct { unsigned int hwrpb$il_mca_record_size; unsigned int hwrpb$il_mca_record_count; } hwrpb$r_mca_size_count_fields; } hwrpb$r_mca_size_count_overlay; unsigned __int64 hwrpb$iq_init_error_record; /* PA INIT err rec buffer */ __union { unsigned __int64 hwrpb$iq_init_record_size_count; __struct { unsigned int hwrpb$il_init_record_size; unsigned int hwrpb$il_init_record_count; } hwrpb$r_init_size_count_fields; } hwrpb$r_init_size_count_overlay; unsigned __int64 hwrpb$iq_cmc_error_record; /* PA CMC err rec buffer */ __union { unsigned __int64 hwrpb$iq_cmc_record_size_count; __struct { unsigned int hwrpb$il_cmc_record_size; unsigned int hwrpb$il_cmc_record_count; } hwrpb$r_cmc_size_count_fields; } hwrpb$r_cmc_size_count_overlay; unsigned __int64 hwrpb$iq_cpe_error_record; /* PA CPE err rec buffer */ __union { unsigned __int64 hwrpb$iq_cpe_record_size_count; __struct { unsigned int hwrpb$il_cpe_record_size; unsigned int hwrpb$il_cpe_record_count; } hwrpb$r_cpe_size_count_fields; } hwrpb$r_cpe_size_count_overlay; unsigned __int64 hwrpb$iq_decon_error_record; /* PA Deconfigured buffer */ __union { unsigned __int64 hwrpb$iq_decon_record_size_cnt; __struct { unsigned int hwrpb$il_decon_record_size; unsigned int hwrpb$il_decon_record_count; } hwrpb$r_decon_size_count_fields; } hwrpb$r_decon_size_count_overlay; /************************************************************************** */ /* [X86-64] SERIAL CONSOLE SUPPORT */ /************************************************************************** */ unsigned __int64 hwrpb$iq_uart_address; /* Console UART PA */ unsigned __int64 hwrpb$iq_debug_uart_pa; /* Debug UART PA */ /* */ /* This next field is valid only when the console is a PCI device */ /* with a PCI Config Header. The overlaid structure has the advantage */ /* of being cast as a PCI_NODE_NUMBER (see PCIDEF.SDL), since its */ /* bitfields are congruent to those in PCI_NODE_NUMBER. */ /* */ __union { /* UART PCI CONFIG */ unsigned __int64 hwrpb$iq_uart_pcicfg_address; __struct { unsigned hwrpb_uart_pcicfg$v_function : 3; unsigned hwrpb_uart_pcicfg$v_device : 5; unsigned hwrpb_uart_pcicfg$v_bus : 8; unsigned hwrpb_uart_pcicfg$v_offset : 16; unsigned hwrpb_uart_pcicfg$v_segment : 8; unsigned hwrpb_uart_pcicfg$v_reserved : 24; } hwrpb$r_uart_pcicfg_address_bits; } hwrpb$r_uart_pcicfg_address_overla; /************************************************************************** */ /* [X86-64] VGA SUPPORT (Unsupported - Ref: GPS$ACPI_SUPPORT) */ /************************************************************************** */ /* This structure can be cast as a PCI_NODE_NUMBER (see PCIDEF.SDL) */ __union { unsigned __int64 hwrpb$iq_vga_pcicfg_address; __struct { unsigned hwrpb_vga_pcicfg$v_function : 3; unsigned hwrpb_vga_pcicfg$v_device : 5; unsigned hwrpb_vga_pcicfg$v_bus : 8; unsigned hwrpb_vga_pcicfg$v_offset : 16; unsigned hwrpb_vga_pcicfg$v_segment : 8; unsigned hwrpb_vga_pcicfg$v_reserved : 24; } hwrpb$r_vga_pcicfg_address; } hwrpb$r_vga_pcicfg_address_overlay; unsigned __int64 hwrpb$iq_vga_tra_offset; /* MMIO TRA */ __union { /* VGA Console Flag */ unsigned __int64 hwrpb$iq_vga_flags; __struct { unsigned hwrpb_vga_flag$v_console : 1; unsigned hwrpb_vga_flag$v_rsvd_flags1 : 31; unsigned hwrpb_vga_flag$v_rsvd_flags2 : 32; } hwrpb$r_vga_flag_bits; } hwrpb$r_vga_flags_overlay; /* */ /* Virtual address of a data structure containing VGA state and data */ /* used to preserve screen contents when moving to SYSBOOT. */ unsigned __int64 hwrpb$iq_vga_state_pointer; /* */ /* Size of the VGA State data structure. The size of the structure is */ /* needed by SYSBOOT for fixup of the VGA_STATE_POINTER when moving */ /* to SYSBOOT. */ unsigned __int64 hwrpb$iq_vga_state_size; /************************************************************************** */ /* [X86-64] ISO INSTALLATION KIT BOOT SUPPORT */ /* */ /* When booting an ISO DVD Installation Kit Image, the entire ISO DVD Image */ /* is transferred from a web server or loaded into memory by the Boot */ /* Manager and becomes memory-resident DMM1 "System Disk" for the duration */ /* of the installation procedure. In order to mount this memory-resident */ /* disk image, its PA and Size are required. */ /************************************************************************** */ /* */ /* Physical address of the ISO Kit Disk Image or ZERO if not used. */ /* */ unsigned __int64 hwrpb$iq_system_memdisk_pa; /* */ /* Size in bytes of the ISO Kit Disk Image or ZERO if not used. */ /* */ unsigned __int64 hwrpb$iq_system_memdisk_size; /************************************************************************** */ /* [X86_64] Fibrechannel and SAS boot device support. */ /* */ /* These values are filled in by the X86 Boot Manager when booting from a */ /* Fibre or SAS system disk. For other disk types, the WWID and WWN fields */ /* will contain ZERO. WWID is typically 16 bytes, but could be larger. */ /************************************************************************** */ /* */ unsigned __int64 hwrpb$iq_bootdev_target_id; /* SCSI Target ID */ unsigned __int64 hwrpb$iq_bootdev_lun; /* Logical Unit Number */ unsigned __int64 hwrpb$iq_bootdev_port_wwn; /* HBA PortID little endian */ unsigned int hwrpb$il_bootdev_wwid_len; /* WWID Length in bytes */ unsigned int hwrpb$il_bootdev_wwid_type; /* WWID Type per WWIDDEF */ /* */ unsigned char hwrpb$b_bootdev_wwid [64]; /* Disk WWID little endian */ /* */ /* Checksum calculated by the Boot Manager and checked by SYSBOOT */ /* */ unsigned __int64 hwrpb$iq_chksum; } HWRPB; #if !defined(__VAXC) #define hwrpb$iq_boot_flags hwrpb$r_boot_flags_overlay.hwrpb$iq_boot_flags #define hwrpb$il_boot_flags_l hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$il_boot_flags\ _l #define hwrpb_boot_flags$v_sysprompt hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\ _flags_field_l.hwrpb_boot_flags$v_sysprompt #define hwrpb_boot_flags$v_xdelta hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\ ags_field_l.hwrpb_boot_flags$v_xdelta #define hwrpb_boot_flags$v_breakpoint hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boo\ t_flags_field_l.hwrpb_boot_flags$v_breakpoint #define hwrpb_boot_flags$v_dk_sda hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\ ags_field_l.hwrpb_boot_flags$v_dk_sda #define hwrpb_boot_flags$v_progress hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\ flags_field_l.hwrpb_boot_flags$v_progress #define hwrpb_boot_flags$v_sysboot hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_sysboot #define hwrpb_boot_flags$v_execinit hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\ flags_field_l.hwrpb_boot_flags$v_execinit #define hwrpb_boot_flags$v_sysinit hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_sysinit #define hwrpb_boot_flags$v_driver hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\ ags_field_l.hwrpb_boot_flags$v_driver #define hwrpb_boot_flags$v_shadow hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\ ags_field_l.hwrpb_boot_flags$v_shadow #define hwrpb_boot_flags$v_netboot hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_netboot #define hwrpb_boot_flags$v_sysdebug hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\ flags_field_l.hwrpb_boot_flags$v_sysdebug #define hwrpb_boot_flags$v_acpi hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_flag\ s_field_l.hwrpb_boot_flags$v_acpi #define hwrpb_boot_flags$v_hw_config hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\ _flags_field_l.hwrpb_boot_flags$v_hw_config #define hwrpb_boot_flags$v_page_faults hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_bo\ ot_flags_field_l.hwrpb_boot_flags$v_page_faults #define hwrpb_boot_flags$v_halt hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_flag\ s_field_l.hwrpb_boot_flags$v_halt #define hwrpb_boot_flags$v_dk_nosysd hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\ _flags_field_l.hwrpb_boot_flags$v_dk_nosysd #define hwrpb_boot_flags$v_x20000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\ ags_field_l.hwrpb_boot_flags$v_x20000 #define hwrpb_boot_flags$v_x40000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\ ags_field_l.hwrpb_boot_flags$v_x40000 #define hwrpb_boot_flags$v_x80000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\ ags_field_l.hwrpb_boot_flags$v_x80000 #define hwrpb_boot_flags$v_x100000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_x100000 #define hwrpb_boot_flags$v_x200000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_x200000 #define hwrpb_boot_flags$v_x400000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_x400000 #define hwrpb_boot_flags$v_opdisplay hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\ _flags_field_l.hwrpb_boot_flags$v_opdisplay #define hwrpb_boot_flags$v_bootmgr hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_bootmgr #define hwrpb_boot_flags$v_memcheck hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\ flags_field_l.hwrpb_boot_flags$v_memcheck #define hwrpb_boot_flags$v_devcheck hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\ flags_field_l.hwrpb_boot_flags$v_devcheck #define hwrpb_boot_flags$v_developer hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\ _flags_field_l.hwrpb_boot_flags$v_developer #define hwrpb_boot_flags$v_mdcheck hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_mdcheck #define hwrpb_boot_flags$v_cpucheck hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\ flags_field_l.hwrpb_boot_flags$v_cpucheck #define hwrpb_boot_flags$v_x40000000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\ _flags_field_l.hwrpb_boot_flags$v_x40000000 #define hwrpb_boot_flags$v_verbose hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\ lags_field_l.hwrpb_boot_flags$v_verbose #define hwrpb$il_boot_flags_h hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_h.hwrpb$il_boot_flags\ _h #define hwrpb_boot_flags$v_root hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_h.hwrpb$r_boot_flag\ s_field_h.hwrpb_boot_flags$v_root #define hwrpb$iq_usb_flags hwrpb$r_usb_bootdev_overlay.hwrpb$iq_usb_flags #define hwrpb_usb$w_vendor_id hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$w_vendor_id #define hwrpb_usb$w_product_id hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$w_product_id #define hwrpb_usb$b_interface_class hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$b_interface_class #define hwrpb_usb$b_interface_subclass hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$b_interface_subclass #define hwrpb_usb$b_interface_protocol hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$b_interface_protocol #define hwrpb_usb$b_serialnum_len hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$b_serialnum_len #define hwrpb$iq_sysvar hwrpb$r_sysvar_overlay.hwrpb$iq_sysvar #define hwrpb$il_sysvar_l hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$il_sysvar_l #define hwrpb_sysvar$v_mpcap hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb\ _sysvar$v_mpcap #define hwrpb_sysvar$v_cnsle hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb\ _sysvar$v_cnsle #define hwrpb_sysvar$v_keyboard hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hw\ rpb_sysvar$v_keyboard #define hwrpb_sysvar$v_dumpboot hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hw\ rpb_sysvar$v_dumpboot #define hwrpb_sysvar$v_graphics hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hw\ rpb_sysvar$v_graphics #define hwrpb_sysvar$v_member_id hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.h\ wrpb_sysvar$v_member_id #define hwrpb_sysvar$ib_vm_type hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hw\ rpb_sysvar$ib_vm_type #define hwrpb_sysvar$ib_vm_config hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.\ hwrpb_sysvar$ib_vm_config #define hwrpb$il_sysvar_h hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$il_sysvar_h #define hwrpb_sysvar$v_fill1 hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$r_sysvar_field3.hwr\ pb_sysvar$v_fill1 #define hwrpb_sysvar$v_rxtx_extent hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$r_sysvar_fiel\ d3.hwrpb_sysvar$v_rxtx_extent #define hwrpb$iq_rxrdy hwrpb$r_rxrdy_overlay.hwrpb$iq_rxrdy #define hwrpb$iq_rxrdy_offset hwrpb$r_rxrdy_overlay.hwrpb$iq_rxrdy_offset #define hwrpb$iq_txrdy hwrpb$r_txrdy_overlay.hwrpb$iq_txrdy #define hwrpb$il_txrdy_l hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$r_txrdy_fields_overlay.hwrpb$il_txrdy_l #define hwrpb_txrdy$v_txrdy_summary hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$r_txrdy_fields_overlay.hwrpb$r_txrdy_field1.hw\ rpb_txrdy$v_txrdy_summary #define hwrpb$il_txrdy_h hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$il_txrdy_h #define hwrpb$iq_bootdev_pcinode hwrpb$r_bootdev_pcinode_overlay.hwrpb$iq_bootdev_pcinode #define hwrpb$il_bootdev_pcinode_l hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay\ .hwrpb$il_bootdev_pcinode_l #define hwrpb_bootdev$v_funct hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay.hwrp\ b$r_bootdev_pcinode_l_fields.hwrpb_bootdev$v_funct #define hwrpb_bootdev$v_device hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay.hwr\ pb$r_bootdev_pcinode_l_fields.hwrpb_bootdev$v_device #define hwrpb_bootdev$v_bus hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay.hwrpb$\ r_bootdev_pcinode_l_fields.hwrpb_bootdev$v_bus #define hwrpb_bootdev$v_hose hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay.hwrpb\ $r_bootdev_pcinode_l_fields.hwrpb_bootdev$v_hose #define hwrpb$il_bootdev_pcinode_h hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_h_overlay\ .hwrpb$il_bootdev_pcinode_h #define hwrpb$il_sysdisk_unit hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_h_overlay.hwrp\ b$il_sysdisk_unit #define hwrpb$iq_altdev_pcinode hwrpb$r_altdev_pcinode_overlay.hwrpb$iq_altdev_pcinode #define hwrpb$il_altdev_pcinode_l hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwr\ pb$il_altdev_pcinode_l #define hwrpb_altdev$v_funct hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwrpb$r_\ altdev_pcinode_l_fields.hwrpb_altdev$v_funct #define hwrpb_altdev$v_device hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwrpb$r\ _altdev_pcinode_l_fields.hwrpb_altdev$v_device #define hwrpb_altdev$v_bus hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwrpb$r_al\ tdev_pcinode_l_fields.hwrpb_altdev$v_bus #define hwrpb_altdev$v_hose hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwrpb$r_a\ ltdev_pcinode_l_fields.hwrpb_altdev$v_hose #define hwrpb$il_altdev_pcinode_h hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$il_altdev_pcinode_h #define hwrpb$iq_cdl_size_count hwrpb$r_cdl_size_count_overlay.hwrpb$iq_cdl_size_count #define hwrpb$il_cdl_size hwrpb$r_cdl_size_count_overlay.hwrpb$r_cdl_size_count_fields.hwrpb$il_cdl_size #define hwrpb$il_cdl_count hwrpb$r_cdl_size_count_overlay.hwrpb$r_cdl_size_count_fields.hwrpb$il_cdl_count #define hwrpb$iq_mca_record_size_count hwrpb$r_mca_size_count_overlay.hwrpb$iq_mca_record_size_count #define hwrpb$il_mca_record_size hwrpb$r_mca_size_count_overlay.hwrpb$r_mca_size_count_fields.hwrpb$il_mca_record_size #define hwrpb$il_mca_record_count hwrpb$r_mca_size_count_overlay.hwrpb$r_mca_size_count_fields.hwrpb$il_mca_record_count #define hwrpb$iq_init_record_size_count hwrpb$r_init_size_count_overlay.hwrpb$iq_init_record_size_count #define hwrpb$il_init_record_size hwrpb$r_init_size_count_overlay.hwrpb$r_init_size_count_fields.hwrpb$il_init_record_size #define hwrpb$il_init_record_count hwrpb$r_init_size_count_overlay.hwrpb$r_init_size_count_fields.hwrpb$il_init_record_count #define hwrpb$iq_cmc_record_size_count hwrpb$r_cmc_size_count_overlay.hwrpb$iq_cmc_record_size_count #define hwrpb$il_cmc_record_size hwrpb$r_cmc_size_count_overlay.hwrpb$r_cmc_size_count_fields.hwrpb$il_cmc_record_size #define hwrpb$il_cmc_record_count hwrpb$r_cmc_size_count_overlay.hwrpb$r_cmc_size_count_fields.hwrpb$il_cmc_record_count #define hwrpb$iq_cpe_record_size_count hwrpb$r_cpe_size_count_overlay.hwrpb$iq_cpe_record_size_count #define hwrpb$il_cpe_record_size hwrpb$r_cpe_size_count_overlay.hwrpb$r_cpe_size_count_fields.hwrpb$il_cpe_record_size #define hwrpb$il_cpe_record_count hwrpb$r_cpe_size_count_overlay.hwrpb$r_cpe_size_count_fields.hwrpb$il_cpe_record_count #define hwrpb$iq_decon_record_size_cnt hwrpb$r_decon_size_count_overlay.hwrpb$iq_decon_record_size_cnt #define hwrpb$il_decon_record_size hwrpb$r_decon_size_count_overlay.hwrpb$r_decon_size_count_fields.hwrpb$il_decon_record_size #define hwrpb$il_decon_record_count hwrpb$r_decon_size_count_overlay.hwrpb$r_decon_size_count_fields.hwrpb$il_decon_record_count #define hwrpb$iq_uart_pcicfg_address hwrpb$r_uart_pcicfg_address_overla.hwrpb$iq_uart_pcicfg_address #define hwrpb_uart_pcicfg$v_function hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_functi\ on #define hwrpb_uart_pcicfg$v_device hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_device #define hwrpb_uart_pcicfg$v_bus hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_bus #define hwrpb_uart_pcicfg$v_offset hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_offset #define hwrpb_uart_pcicfg$v_segment hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_segment #define hwrpb_uart_pcicfg$v_reserved hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_reserv\ ed #define hwrpb$iq_vga_pcicfg_address hwrpb$r_vga_pcicfg_address_overlay.hwrpb$iq_vga_pcicfg_address #define hwrpb_vga_pcicfg$v_function hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_function #define hwrpb_vga_pcicfg$v_device hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_device #define hwrpb_vga_pcicfg$v_bus hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_bus #define hwrpb_vga_pcicfg$v_offset hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_offset #define hwrpb_vga_pcicfg$v_segment hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_segment #define hwrpb_vga_pcicfg$v_reserved hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_reserved #define hwrpb$iq_vga_flags hwrpb$r_vga_flags_overlay.hwrpb$iq_vga_flags #define hwrpb_vga_flag$v_console hwrpb$r_vga_flags_overlay.hwrpb$r_vga_flag_bits.hwrpb_vga_flag$v_console #define hwrpb_vga_flag$v_rsvd_flags1 hwrpb$r_vga_flags_overlay.hwrpb$r_vga_flag_bits.hwrpb_vga_flag$v_rsvd_flags1 #define hwrpb_vga_flag$v_rsvd_flags2 hwrpb$r_vga_flags_overlay.hwrpb$r_vga_flag_bits.hwrpb_vga_flag$v_rsvd_flags2 #endif /* #if !defined(__VAXC) */ /************ END OF X86_64 HWRPB STRUCTURE ***************************** */ #define HWRPB$C_LENGTH 1376 /* Length of HWRPB */ #define HWRPB$K_LENGTH 1376 /* Length of HWRPB */ #define HWRPB$S_HWRPBDEF 1376 /* Old size name - synonym */ /************************************************************************ */ /* HWPCB structure in Per-CPU slot definitions - zero relative */ /************************************************************************ */ #define HWPCB$M_ASTEN 0xF #define HWPCB$M_ASTSR 0xF0 #define HWPCB$M_ASTEN_KEN 0x1 #define HWPCB$M_ASTEN_EEN 0x2 #define HWPCB$M_ASTEN_SEN 0x4 #define HWPCB$M_ASTEN_UEN 0x8 #define HWPCB$M_ASTSR_KPD 0x10 #define HWPCB$M_ASTSR_EPD 0x20 #define HWPCB$M_ASTSR_SPD 0x40 #define HWPCB$M_ASTSR_UPD 0x80 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hwpcb { /*************** */ /* Base of HWPCB */ /*************** */ #pragma __nomember_alignment __union { unsigned __int64 hwpcb$iq_hwpcb_base; /********************** */ /* Kernel Stack Pointer */ /********************** */ __union { unsigned __int64 hwpcb$iq_ksp; __struct { unsigned int hwpcb$il_ksp_l; unsigned int hwpcb$il_ksp_h; } hwpcb$r_ksp_fields; } hwpcb$r_ksp_overlay; } hwpcb$r_hwpcb_overlay; /************************* */ /* Executive Stack Pointer */ /************************* */ __union { unsigned __int64 hwpcb$iq_esp; __struct { unsigned int hwpcb$il_esp_l; unsigned int hwpcb$il_esp_h; } hwpcb$r_esp_fields; } hwpcb$r_esp_overlay; /************************** */ /* Supervisor Stack Pointer */ /************************** */ __union { unsigned __int64 hwpcb$iq_ssp; __struct { unsigned int hwpcb$il_ssp_l; unsigned int hwpcb$il_ssp_h; } hwpcb$r_ssp_fields; } hwpcb$r_ssp_overlay; /******************** */ /* User Stack Pointer */ /******************** */ __union { unsigned __int64 hwpcb$iq_usp; __struct { unsigned int hwpcb$il_usp_l; unsigned int hwpcb$il_usp_h; } hwpcb$r_usp_fields; } hwpcb$r_usp_overlay; /***************** */ /* Page Table Base */ /***************** */ unsigned __int64 hwpcb$iq_ptbr [4]; /* One per mode */ /***** */ /* ASN */ /***** */ unsigned __int64 hwpcb$iq_asn; /**************************************************** */ /* AST Enable and Summary Registers (ASTSR and ASTEN) */ /**************************************************** */ __union { unsigned __int64 hwpcb$iq_astsr_asten; __struct { unsigned int hwpcb$il_ast_l; unsigned int hwpcb$il_ast_h; } hwpcb$r_ast_fields; __struct { unsigned hwpcb$v_asten : 4; /* AST Enable Register */ unsigned hwpcb$v_astsr : 4; /* AST Pending Summary Register */ } hwpcb$r_ast_bits0; __struct { unsigned hwpcb$v_asten_ken : 1; /* Kernel AST Enable = 1 */ unsigned hwpcb$v_asten_een : 1; /* Executive AST Enable = 1 */ unsigned hwpcb$v_asten_sen : 1; /* Supervisor AST Enable = 1 */ unsigned hwpcb$v_asten_uen : 1; /* User AST Enable = 1 */ unsigned hwpcb$v_astsr_kpd : 1; /* Kernel AST Pending = 1 */ unsigned hwpcb$v_astsr_epd : 1; /* Executive AST Pending = 1 */ unsigned hwpcb$v_astsr_spd : 1; /* Supervisor AST Pending = 1 */ unsigned hwpcb$v_astsr_upd : 1; /* User AST Pending = 1 */ } hwpcb$r_ast_bits1; } hwpcb$r_ast_overlay; /**************************** */ /* Process Attributes Section */ /**************************** */ unsigned __int64 hwpcb$iq_perf_control; /*************** */ /* Cycle Counter */ /*************** */ __union { unsigned __int64 hwpcb$iq_cc; __struct { unsigned int hwpcb$il_cc_l; unsigned int hwpcb$il_cc_h; } hwpcb$r_cc_fields; } hwpcb$r_cc_overlay; /********************** */ /* Process Unique Value - IA64 Thread Pointer (R13) */ /********************** */ __union { unsigned __int64 hwpcb$iq_unq; /* Process Unique Value */ __struct { unsigned int hwpcb$il_unq_l; unsigned int hwpcb$il_unq_h; } hwpcb$r_unq_fields; } hwpcb$r_unq_overlay; /*********************** */ /* Alpha register blocks */ /*********************** */ #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwpcb$pq_alphareg [4]; #else unsigned __int64 hwpcb$pq_alphareg [4]; #endif /*************** */ /* Previous mode */ /*************** */ unsigned char hwpcb$b_pmod; /* Previous mode */ unsigned char hwpcb$b_was_scheduled; char hwpcb$b_reserved_1 [6]; /* Reserved for future use */ /***************** */ /* Interrupt depth */ /***************** */ unsigned int hwpcb$il_interrupt_depth; /* Interrupt depth */ /*************** */ /* Current frame */ /*************** */ int hwpcb$l_cur_frame_mode; /* Mode of currently active frame */ #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwpcb$pq_cur_frame; /* Currently active frame */ #else unsigned __int64 hwpcb$pq_cur_frame; #endif /********************* */ /* Kernel Stack Limits */ /********************* */ unsigned __int64 hwpcb$q_kstack_top; unsigned __int64 hwpcb$q_kstack_bottom; /****************************** */ /* Reserved for PALcode scratch */ /****************************** */ __int64 hwpcb$iq_pal_rsvd [5]; /* Reserved for PAL scratch */ } HWPCB; #if !defined(__VAXC) #define hwpcb$iq_hwpcb_base hwpcb$r_hwpcb_overlay.hwpcb$iq_hwpcb_base #define hwpcb$iq_ksp hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$iq_ksp #define hwpcb$il_ksp_l hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$r_ksp_fields.hwpcb$il_ksp_l #define hwpcb$il_ksp_h hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$r_ksp_fields.hwpcb$il_ksp_h #define hwpcb$iq_esp hwpcb$r_esp_overlay.hwpcb$iq_esp #define hwpcb$il_esp_l hwpcb$r_esp_overlay.hwpcb$r_esp_fields.hwpcb$il_esp_l #define hwpcb$il_esp_h hwpcb$r_esp_overlay.hwpcb$r_esp_fields.hwpcb$il_esp_h #define hwpcb$iq_ssp hwpcb$r_ssp_overlay.hwpcb$iq_ssp #define hwpcb$il_ssp_l hwpcb$r_ssp_overlay.hwpcb$r_ssp_fields.hwpcb$il_ssp_l #define hwpcb$il_ssp_h hwpcb$r_ssp_overlay.hwpcb$r_ssp_fields.hwpcb$il_ssp_h #define hwpcb$iq_usp hwpcb$r_usp_overlay.hwpcb$iq_usp #define hwpcb$il_usp_l hwpcb$r_usp_overlay.hwpcb$r_usp_fields.hwpcb$il_usp_l #define hwpcb$il_usp_h hwpcb$r_usp_overlay.hwpcb$r_usp_fields.hwpcb$il_usp_h #define hwpcb$iq_astsr_asten hwpcb$r_ast_overlay.hwpcb$iq_astsr_asten #define hwpcb$il_ast_l hwpcb$r_ast_overlay.hwpcb$r_ast_fields.hwpcb$il_ast_l #define hwpcb$il_ast_h hwpcb$r_ast_overlay.hwpcb$r_ast_fields.hwpcb$il_ast_h #define hwpcb$v_asten hwpcb$r_ast_overlay.hwpcb$r_ast_bits0.hwpcb$v_asten #define hwpcb$v_astsr hwpcb$r_ast_overlay.hwpcb$r_ast_bits0.hwpcb$v_astsr #define hwpcb$v_asten_ken hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_ken #define hwpcb$v_asten_een hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_een #define hwpcb$v_asten_sen hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_sen #define hwpcb$v_asten_uen hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_uen #define hwpcb$v_astsr_kpd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_kpd #define hwpcb$v_astsr_epd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_epd #define hwpcb$v_astsr_spd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_spd #define hwpcb$v_astsr_upd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_upd #define hwpcb$iq_cc hwpcb$r_cc_overlay.hwpcb$iq_cc #define hwpcb$il_cc_l hwpcb$r_cc_overlay.hwpcb$r_cc_fields.hwpcb$il_cc_l #define hwpcb$il_cc_h hwpcb$r_cc_overlay.hwpcb$r_cc_fields.hwpcb$il_cc_h #define hwpcb$iq_unq hwpcb$r_unq_overlay.hwpcb$iq_unq #define hwpcb$il_unq_l hwpcb$r_unq_overlay.hwpcb$r_unq_fields.hwpcb$il_unq_l #define hwpcb$il_unq_h hwpcb$r_unq_overlay.hwpcb$r_unq_fields.hwpcb$il_unq_h #endif /* #if !defined(__VAXC) */ /* */ #define HWPCB$C_LENGTH 216 /* Full length of HWPCB$ */ #define HWPCB$K_LENGTH 216 /* Full length of HWPCB$ */ #define HWPCB$S_HWPCBDEF 216 /* Old size name - synonym */ /************************************************************************** */ /* Per-CPU slot definitions */ /************************************************************************** */ #define SLOT$M_BIP 0x1 #define SLOT$M_RC 0x2 #define SLOT$M_PA 0x4 #define SLOT$M_PP 0x8 #define SLOT$M_OH 0x10 #define SLOT$M_CV 0x20 #define SLOT$M_PV 0x40 #define SLOT$M_PMV 0x80 #define SLOT$M_PL 0x100 #define SLOT$M_RIP 0x200 #define SLOT$M_HLTREQ 0xFF0000 #define HWRPB_HALT$K_NO_ACTION 0 /* Just Halt */ #define HWRPB_HALT$K_SAVE_RESTORE_TERM 1 /* Save or restore term */ #define HWRPB_HALT$K_COLD_REBOOT 2 /* Cold bootstrap request */ #define HWRPB_HALT$K_WARM_REBOOT 3 /* Warm bootstrap request */ #define HWRPB_HALT$K_REMAIN_HALTED 4 /* Don't restart */ #define HWRPB_HALT$K_POWEROFF 5 /* Power-off system */ /* reserved */ #define HWRPB_HALT$K_MIGRATE 7 /* Galaxy CPU migration */ /* reserved */ #define HWRPB_HALT$K_BIB_STATE 9 /* Invoke ACPI state for BIB state */ #define SLOT$M_PARTID 0xFFFF #define HWRPB_PAL_REV$K_IPF 32 /* Standard PAL code */ /**************** */ #define HWRPB_CPU_TYPE$K_MERCED 7 #define HWRPB_CPU_TYPE$K_MCKINLEY 31 /********************* */ #define SLOT$M_VAX_FP 0x1 #define SLOT$M_IEEE_FP 0x2 #define SLOT$M_PE 0x4 #define HWRPB$K_RESTART 0 /* Btstrap,procr strt, or pwrfl. */ #define HWRPB$K_CRASH_CMD 1 /* Crash via cosole request */ #define HWRPB$K_KSP_NOT_VALID 2 /* Kernel stack not valid halt */ #define HWRPB$K_INVALID_SCBB 3 /* Invalid SCB Base register */ #define HWRPB$K_INVALID_PTBR 4 /* Invalid Page Table Base Reg. */ #define HWRPB$K_CALL_PAL_HALT 5 /* Processor executed in ker. mode */ #define HWRPB$K_DOUBLE_ERROR 6 /* Double error abort */ #define HWRPB$K_MCHECK_IN_PAL 7 /* Mcheck in PAL environment */ #define HWRPB$K_LAST_HALT_REASON 7 /*********************** */ #define SLOT$M_MCES_MCA 0x1 #define SLOT$M_MCES_CPE 0x2 #define SLOT$M_MCES_CMC 0x4 #define SLOT$M_MCES_CPE_DIS 0x8 #define SLOT$M_MCES_CMC_DIS 0x10 #define SLOT$M_MCES_INIT 0x20 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _cpu_slot { /******************** */ /* Restart/Boot HWPCB */ /******************** */ #pragma __nomember_alignment unsigned __int64 slot$iq_hwpcb [32]; /* HWPCB rounded to multiple of 128 */ /************************************ */ /* Physical offset from slot to HWRPB */ /************************************ */ unsigned __int64 slot$iq_hwrpb_offset; /* Offset to HWRPB Negative */ /******************** */ /* Per-CPU state bits */ /******************** */ __union { unsigned __int64 slot$iq_state; __struct { __union { unsigned int slot$il_state; __struct { unsigned slot$v_bip : 1; /* Bootstrap in progress */ unsigned slot$v_rc : 1; /* Restart capable */ unsigned slot$v_pa : 1; /* Processor available */ unsigned slot$v_pp : 1; /* Processor present */ unsigned slot$v_oh : 1; /* Operator halted */ unsigned slot$v_cv : 1; /* Context valid */ unsigned slot$v_pv : 1; /* PAL code valid */ unsigned slot$v_pmv : 1; /* PAL code memory valid */ unsigned slot$v_pl : 1; /* PAL code loaded */ unsigned slot$v_rip : 1; /* Rendezvous in progress */ unsigned slot$v_state_fill1 : 6 /** WARNING: bitfield array has been reduced to a string **/ ; unsigned slot$v_hltreq : 8; unsigned slot$v_fill2 : 8 /** WARNING: bitfield array has been reduced to a string **/ ; } slot$r_state_field1; } slot$r_state_fields_overlay; __union { unsigned int slot$il_state_h; __struct { unsigned slot$v_partid : 16; unsigned slot$v_fill3 : 16 /** WARNING: bitfield array has been reduced to a string **/ ; } slot$r_state_field2; } slot$r_state_fields2_overlay; } slot$r_state_fields; } slot$r_state_overlay; /************************************** */ /* Physical Address of SAL memory space */ /************************************** */ __union { unsigned __int64 slot$iq_sal_mem_pa; __struct { unsigned int slot$il_sal_mem_pa_l; unsigned int slot$il_sal_mem_pa_h; } slot$r_sal_mem_pa_fields; } slot$r_sal_mem_pa_overlay; /************************************** */ /* Physical Address of PAL memory space */ /************************************** */ __union { unsigned __int64 slot$iq_pal_mem_pa; __struct { unsigned int slot$il_pal_mem_pa_l; unsigned int slot$il_pal_mem_pa_h; } slot$r_pal_mem_pa_fields; } slot$r_pal_mem_pa_overlay; /**************************************** */ /* PALcode revision required by processor */ /**************************************** */ __union { unsigned __int64 slot$iq_pal_rev; __struct { __union { unsigned int slot$il_pal_rev_l; __struct { unsigned char slot$b_pal_min_rev; /* PAL code minor revision */ unsigned char slot$b_pal_maj_rev; /* PAL code major revision */ unsigned char slot$b_pal_var; /* PAL code variation */ char slot$b_palrev_fill1 [1]; } slot$r_pal_rev_l_fields; } slot$r_pal_rev_fields1_overlay; __union { unsigned int slot$il_pal_rev_h; __struct { unsigned short int slot$iw_pal_compt; /* PAL code compatibility */ unsigned short int slot$iw_max_share; /* Max number CPUs to share */ } slot$r_pal_rev_h_fields; } slot$r_pal_rev_fields_h_overlay; } slot$r_pal_rev_fields; } slot$r_pal_rev_overlay; /* Processor Type */ /**************** */ __union { unsigned __int64 slot$iq_cpu_type; __struct { unsigned int slot$il_cpu_type_l; unsigned int slot$il_cpu_type_h; } slot$r_cpu_type_fields; } slot$r_cpu_type_overlay; /* Processor Variation */ /********************* */ __union { unsigned __int64 slot$iq_cpu_var; __struct { __union { unsigned int slot$il_cpu_var_l; __struct { unsigned slot$v_vax_fp : 1; /* VAX floating point */ unsigned slot$v_ieee_fp : 1; /* IEEE floating point */ unsigned slot$v_pe : 1; /* Processor Eligibility */ unsigned slot$v_cpuvar_fill1 : 29 /** WARNING: bitfield array has been reduced to a string **/ ; } slot$r_cpu_var_field1; } slot$r_cpu_var_fields_overlay; unsigned int slot$il_cpu_var_h; } slot$r_cpu_var_fields; } slot$r_cpu_var_overlay; /***************************** */ /* Processor Stepping Revision */ /***************************** */ __union { unsigned __int64 slot$iq_cpu_rev; __struct { unsigned int slot$il_cpu_rev_l; unsigned int slot$il_cpu_rev_h; } slot$r_cpu_rev_fields; } slot$r_cpu_rev_overlay; /******************* */ /* CPU serial number */ /******************* */ unsigned char slot$b_cpu_serialnum [16]; /********************************* */ /* Physical Address of logout area */ /********************************* */ __union { unsigned __int64 slot$iq_logout_pa; __struct { unsigned int slot$il_logout_pa_l; unsigned int slot$il_logout_pa_h; } slot$r_logout_pa_fields; } slot$r_logout_pa_overlay; /********************* */ /* Size of logout area */ /********************* */ __union { unsigned __int64 slot$iq_logout_len; __struct { unsigned int slot$il_logout_len_l; unsigned int slot$il_logout_len_h; } slot$r_logout_len_fields; } slot$r_logout_len_overlay; /*********** */ /* Halt PCBB */ /*********** */ __union { unsigned __int64 slot$iq_halt_pcbb; __struct { unsigned int slot$il_halt_pcbb_l; unsigned int slot$il_halt_pcbb_h; } slot$r_halt_pcbb_fields; } slot$r_halt_pcbb_overlay; /********* */ /* Halt PC */ /********* */ __union { unsigned __int64 slot$iq_halt_pc; __struct { unsigned int slot$il_halt_pc_l; unsigned int slot$il_halt_pc_h; } slot$r_halt_pc_fields; } slot$r_halt_pc_overlay; /********* */ /* Halt PS */ /********* */ __union { unsigned __int64 slot$iq_halt_ps; __struct { unsigned int slot$il_halt_ps_l; unsigned int slot$il_halt_ps_h; } slot$r_halt_ps_fields; } slot$r_halt_ps_overlay; /******************** */ /* Halt Argument List */ /******************** */ __union { unsigned __int64 slot$iq_halt_arg; __struct { unsigned int slot$il_halt_arg_l; unsigned int slot$il_halt_arg_h; } slot$r_halt_arg_fields; } slot$r_halt_arg_overlay; /********************* */ /* Halt Return Address */ /********************* */ __union { unsigned __int64 slot$iq_halt_ret; __struct { unsigned int slot$il_halt_ret_l; unsigned int slot$il_halt_ret_h; } slot$r_halt_ret_fields; } slot$r_halt_ret_overlay; /********************** */ /* Halt Procedure Value */ /********************** */ __union { unsigned __int64 slot$iq_halt_pv; __struct { unsigned int slot$il_halt_pv_l; unsigned int slot$il_halt_pv_h; } slot$r_halt_pv_fields; } slot$r_halt_pv_overlay; /*********** */ /* Halt Code */ /*********** */ __union { unsigned __int64 slot$iq_haltcode; __struct { unsigned int slot$il_haltcode_l; unsigned int slot$il_haltcode_h; } slot$r_haltcode_fields; } slot$r_haltcode_overlay; /* Reserved for Software */ /*********************** */ __union { unsigned __int64 slot$iq_soft_flags; /* Reserved to software */ __struct { unsigned int slot$il_soft_flags_l; unsigned int slot$il_soft_flags_h; } slot$r_soft_flags_fields; } slot$r_soft_flags_overlay; /************************************ */ /* Interprocessor Console Buffer Area */ /************************************ */ __union { unsigned char slot$b_incon_buf_area [168]; /* SMP Console Buf Area */ __struct { unsigned int slot$il_rxlen; unsigned int slot$il_txlen; unsigned char slot$b_rxbuffer [80]; unsigned char slot$b_txbuffer [80]; } slot$r_incon_buf_fields; } slot$r_incon_buf_overlay; /*********************************************** */ /* The next 16 quadwords are reserved for the */ /* "PALcode Revisions Available Block". */ /* The format of the first quadword is platform specific. */ /* The format of each subsequent quadword follows the */ /* PALcode revision field (SLOT[168]) */ /*********************************************** */ unsigned __int64 slot$q_pal_rev_avail [16]; /* PALcode Revisions Available Block */ /********************************** */ /* Processor Software Compatibility */ /********************************** */ __union { unsigned __int64 slot$iq_cpu_sw_comp; __struct { unsigned int slot$il_cpu_sw_comp_l; unsigned int slot$il_cpu_sw_comp_h; } slot$r_cpu_sw_comp_fields; } slot$r_cpu_sw_comp_overlay; /*************************** */ /* Console Frame Data Buffer */ /*************************** */ __union { unsigned __int64 slot$iq_console_data_pa; __struct { unsigned int slot$il_console_data_pa_l; unsigned int slot$il_console_data_pa_h; } slot$r_console_data_pa_fields; } slot$r_console_data_pa_overlay; /******************************** */ /* Console Frame Data Buffer Size */ /******************************** */ __union { unsigned __int64 slot$iq_console_data_size; __struct { unsigned int slot$il_console_data_size_l; unsigned int slot$il_console_data_size_h; } slot$r_console_data_size_fields; } slot$r_console_data_size_overlay; /******************* */ /* Cache Information */ /******************* */ __union { unsigned __int64 slot$iq_cpu_cache; __struct { __union { unsigned int slot$il_cpu_cache_l; /* CPU_CACHE_FIELD1 structure fill; */ /* CPU_CACHE_ASSOC_DEGREE byte unsigned; /* Degree of set associativity */ /* CPU_CACHE_FIELD2 structure fill; */ /* CPU_CACHE_WRITE_BACK bitfield mask; /* Write-back or Write-through */ /* CPU_CACHE_FILL1 bitfield dimension 7 fill; */ /* end CPU_CACHE_FIELD2; */ /* CPU_CACHE_BLOCK_SIZE integer_word unsigned; /* Size of individual cache block */ /* end CPU_CACHE_FIELD1; */ } slot$r_cpu_cache_fields_overlay; unsigned int slot$il_cpu_cache_h; /* Total size of cache in kb */ } slot$r_cpu_cache_fields; } slot$r_cpu_cache_overlay; /************************* */ /* Cycle Counter Frequency */ /************************* */ __union { unsigned __int64 slot$iq_cycle_count_freq; __struct { unsigned int slot$il_cycle_count_freq_l; unsigned int slot$il_cycle_count_freq_h; } slot$r_cycle_count_freq_fields; } slot$r_cycle_count_freq_overlay; /*************************** */ /* Clock Interrupt Frequency */ /*************************** */ __union { unsigned __int64 slot$iq_clock_int_freq; __struct { unsigned int slot$il_clock_int_freq_l; unsigned int slot$il_clock_int_freq_h; } slot$r_clock_int_freq_fields; } slot$r_clock_int_freq_overlay; /*************** */ /* ITC Frequency */ /*************** */ unsigned __int64 slot$iq_itc_freq; /***************** */ /* ITC Drift value */ /***************** */ unsigned __int64 slot$iq_itc_drift; /* Hardware drift in ppm clock ticks */ /************************ */ /* LID - IPF CPU Local ID */ /************************ */ unsigned __int64 slot$iq_lid; /* CPU Local ID used for intr generation */ /****************************** */ /* Translation buffer registers */ /****************************** */ unsigned __int64 slot$q_tbreg_init [8]; /* Values to stuff into TB registers (0=unused) */ /************************************* */ /* Kernel Register Values for this CPU */ /************************************* */ unsigned __int64 slot$q_kreg_init [8]; /* Values to stuff into kernel registers (0=unused) */ /******************************** */ /* Interrupt Vector Table Address */ /******************************** */ #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_ivt_init; /* VA of the interrupt vector table for this CPU */ #else unsigned __int64 slot$pq_ivt_init; #endif /************************************** */ /* Virtual Hash Page Table for this CPU */ /************************************** */ unsigned __int64 slot$iq_swis_offset; /* VA of VHPT for this CPU (0 means VHPT is disabled) */ /*********************** */ /* Interrupt Stack Bases */ /*********************** */ unsigned __int64 slot$q_isp_base; /* The interrupt stack pointer base */ unsigned __int64 slot$q_ibsp_base; /* The interrupt stack RSE backing store pointer base */ /********************************************** */ /* Stack pointers for hardware interrupt events */ /********************************************** */ #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_mca_ksp; /* MCA Kernel Stack */ #else unsigned __int64 slot$pq_mca_ksp; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_init_ksp; /* Init Kernel Stack */ #else unsigned __int64 slot$pq_init_ksp; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_cmc_ksp; /* CMC Kernel Stack */ #else unsigned __int64 slot$pq_cmc_ksp; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_cpe_ksp; /* CPE Kernel Stack */ #else unsigned __int64 slot$pq_cpe_ksp; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_mca_bsp; /* MCA Backing Store Pointer */ #else unsigned __int64 slot$pq_mca_bsp; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_init_bsp; /* Init Backing Store Pointer */ #else unsigned __int64 slot$pq_init_bsp; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_cmc_bsp; /* CMC Backing Store Pointer */ #else unsigned __int64 slot$pq_cmc_bsp; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_cpe_bsp; /* CPE Backing Store Pointer */ #else unsigned __int64 slot$pq_cpe_bsp; #endif /************************************************** */ /* Emulated Machine Check Error Summary cell (MCES) */ /************************************************** */ __union { unsigned __int64 slot$q_mces; __struct { unsigned slot$v_mces_mca : 1; unsigned slot$v_mces_cpe : 1; unsigned slot$v_mces_cmc : 1; unsigned slot$v_mces_cpe_dis : 1; unsigned slot$v_mces_cmc_dis : 1; unsigned slot$v_mces_init : 1; unsigned slot$v_fill_0_ : 2; } slot$r_mces_fields; } slot$r_mces_overlay; /*************************** */ /* ACPI Processor Identifier */ /*************************** */ __union { unsigned __int64 slot$iq_acpi_id; __struct { unsigned int slot$il_acpi_id_l; unsigned int slot$il_acpi_id_h; } slot$r_acpi_id_fields; } slot$r_acpi_id_overlay; /********************************** */ /* ACPI Processor Unique Identifier */ /********************************** */ __union { #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_acpi_uid; #else unsigned __int64 slot$pq_acpi_uid; #endif #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif void *slot$ps_acpi_uid_l; } slot$r_acpi_uid_overlay; /********************************************** */ /* Handle to Processor Object in ACPI Namespace */ /********************************************** */ unsigned __int64 slot$iq_acpi_handle; /************************** */ /* System Firmware Revision */ /************************** */ __union { unsigned __int64 slot$iq_sys_fw_rev; __struct { unsigned short int slot$iw_sys_fw_min_rev; unsigned short int slot$iw_sys_fw_maj_rev; char slot$b_fwrev_fill1 [4]; } slot$r_sys_fw_fields; } slot$r_sys_fw_rev_overlay; /********************************************************* */ /* Baseboard Management Controller (BMC) Firmware Revision */ /********************************************************* */ __union { unsigned __int64 slot$iq_bmc_fw_rev; __struct { unsigned short int slot$iw_bmc_fw_min_rev; unsigned short int slot$iw_bmc_fw_maj_rev; char slot$b_bmcfw_fill1 [4]; } slot$r_bmc_fw_fields; } slot$r_bmc_fw_rev_overlay; /**************************************** */ /* Management Port (MP) Firmware Revision */ /**************************************** */ __union { unsigned __int64 slot$iq_mp_fw_rev; __struct { unsigned short int slot$iw_mp_fw_min_rev; unsigned short int slot$iw_mp_fw_maj_rev; char slot$b_mpfw_fill1 [4]; } slot$r_mp_fw_fields; } slot$r_mp_fw_rev_overlay; /************************** */ /* Base Processor Frequency */ /************************** */ unsigned __int64 slot$iq_base_proc_freq; /* true max CPU speed */ } CPU_SLOT; #if !defined(__VAXC) #define slot$iq_state slot$r_state_overlay.slot$iq_state #define slot$il_state slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$il_state #define slot$v_bip slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_bip #define slot$v_rc slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_rc #define slot$v_pa slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pa #define slot$v_pp slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pp #define slot$v_oh slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_oh #define slot$v_cv slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_cv #define slot$v_pv slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pv #define slot$v_pmv slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pmv #define slot$v_pl slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pl #define slot$v_rip slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_rip #define slot$v_hltreq slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_hltreq #define slot$il_state_h slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields2_overlay.slot$il_state_h #define slot$v_partid slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields2_overlay.slot$r_state_field2.slot$v_partid #define slot$iq_sal_mem_pa slot$r_sal_mem_pa_overlay.slot$iq_sal_mem_pa #define slot$il_sal_mem_pa_l slot$r_sal_mem_pa_overlay.slot$r_sal_mem_pa_fields.slot$il_sal_mem_pa_l #define slot$il_sal_mem_pa_h slot$r_sal_mem_pa_overlay.slot$r_sal_mem_pa_fields.slot$il_sal_mem_pa_h #define slot$iq_pal_mem_pa slot$r_pal_mem_pa_overlay.slot$iq_pal_mem_pa #define slot$il_pal_mem_pa_l slot$r_pal_mem_pa_overlay.slot$r_pal_mem_pa_fields.slot$il_pal_mem_pa_l #define slot$il_pal_mem_pa_h slot$r_pal_mem_pa_overlay.slot$r_pal_mem_pa_fields.slot$il_pal_mem_pa_h #define slot$iq_pal_rev slot$r_pal_rev_overlay.slot$iq_pal_rev #define slot$il_pal_rev_l slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$il_pal_rev_l #define slot$b_pal_min_rev slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$r_pal_rev_l_fields.slot\ $b_pal_min_rev #define slot$b_pal_maj_rev slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$r_pal_rev_l_fields.slot\ $b_pal_maj_rev #define slot$b_pal_var slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$r_pal_rev_l_fields.slot$b_p\ al_var #define slot$il_pal_rev_h slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$il_pal_rev_h #define slot$iw_pal_compt slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$r_pal_rev_h_fields.slot\ $iw_pal_compt #define slot$iw_max_share slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$r_pal_rev_h_fields.slot\ $iw_max_share #define slot$iq_cpu_type slot$r_cpu_type_overlay.slot$iq_cpu_type #define slot$il_cpu_type_l slot$r_cpu_type_overlay.slot$r_cpu_type_fields.slot$il_cpu_type_l #define slot$il_cpu_type_h slot$r_cpu_type_overlay.slot$r_cpu_type_fields.slot$il_cpu_type_h #define slot$iq_cpu_var slot$r_cpu_var_overlay.slot$iq_cpu_var #define slot$il_cpu_var_l slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$il_cpu_var_l #define slot$v_vax_fp slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_vax_fp #define slot$v_ieee_fp slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_ieee\ _fp #define slot$v_pe slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_pe #define slot$il_cpu_var_h slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$il_cpu_var_h #define slot$iq_cpu_rev slot$r_cpu_rev_overlay.slot$iq_cpu_rev #define slot$il_cpu_rev_l slot$r_cpu_rev_overlay.slot$r_cpu_rev_fields.slot$il_cpu_rev_l #define slot$il_cpu_rev_h slot$r_cpu_rev_overlay.slot$r_cpu_rev_fields.slot$il_cpu_rev_h #define slot$iq_logout_pa slot$r_logout_pa_overlay.slot$iq_logout_pa #define slot$il_logout_pa_l slot$r_logout_pa_overlay.slot$r_logout_pa_fields.slot$il_logout_pa_l #define slot$il_logout_pa_h slot$r_logout_pa_overlay.slot$r_logout_pa_fields.slot$il_logout_pa_h #define slot$iq_logout_len slot$r_logout_len_overlay.slot$iq_logout_len #define slot$il_logout_len_l slot$r_logout_len_overlay.slot$r_logout_len_fields.slot$il_logout_len_l #define slot$il_logout_len_h slot$r_logout_len_overlay.slot$r_logout_len_fields.slot$il_logout_len_h #define slot$iq_halt_pcbb slot$r_halt_pcbb_overlay.slot$iq_halt_pcbb #define slot$il_halt_pcbb_l slot$r_halt_pcbb_overlay.slot$r_halt_pcbb_fields.slot$il_halt_pcbb_l #define slot$il_halt_pcbb_h slot$r_halt_pcbb_overlay.slot$r_halt_pcbb_fields.slot$il_halt_pcbb_h #define slot$iq_halt_pc slot$r_halt_pc_overlay.slot$iq_halt_pc #define slot$il_halt_pc_l slot$r_halt_pc_overlay.slot$r_halt_pc_fields.slot$il_halt_pc_l #define slot$il_halt_pc_h slot$r_halt_pc_overlay.slot$r_halt_pc_fields.slot$il_halt_pc_h #define slot$iq_halt_ps slot$r_halt_ps_overlay.slot$iq_halt_ps #define slot$il_halt_ps_l slot$r_halt_ps_overlay.slot$r_halt_ps_fields.slot$il_halt_ps_l #define slot$il_halt_ps_h slot$r_halt_ps_overlay.slot$r_halt_ps_fields.slot$il_halt_ps_h #define slot$iq_halt_arg slot$r_halt_arg_overlay.slot$iq_halt_arg #define slot$il_halt_arg_l slot$r_halt_arg_overlay.slot$r_halt_arg_fields.slot$il_halt_arg_l #define slot$il_halt_arg_h slot$r_halt_arg_overlay.slot$r_halt_arg_fields.slot$il_halt_arg_h #define slot$iq_halt_ret slot$r_halt_ret_overlay.slot$iq_halt_ret #define slot$il_halt_ret_l slot$r_halt_ret_overlay.slot$r_halt_ret_fields.slot$il_halt_ret_l #define slot$il_halt_ret_h slot$r_halt_ret_overlay.slot$r_halt_ret_fields.slot$il_halt_ret_h #define slot$iq_halt_pv slot$r_halt_pv_overlay.slot$iq_halt_pv #define slot$il_halt_pv_l slot$r_halt_pv_overlay.slot$r_halt_pv_fields.slot$il_halt_pv_l #define slot$il_halt_pv_h slot$r_halt_pv_overlay.slot$r_halt_pv_fields.slot$il_halt_pv_h #define slot$iq_haltcode slot$r_haltcode_overlay.slot$iq_haltcode #define slot$il_haltcode_l slot$r_haltcode_overlay.slot$r_haltcode_fields.slot$il_haltcode_l #define slot$il_haltcode_h slot$r_haltcode_overlay.slot$r_haltcode_fields.slot$il_haltcode_h #define slot$iq_soft_flags slot$r_soft_flags_overlay.slot$iq_soft_flags #define slot$il_soft_flags_l slot$r_soft_flags_overlay.slot$r_soft_flags_fields.slot$il_soft_flags_l #define slot$il_soft_flags_h slot$r_soft_flags_overlay.slot$r_soft_flags_fields.slot$il_soft_flags_h #define slot$b_incon_buf_area slot$r_incon_buf_overlay.slot$b_incon_buf_area #define slot$il_rxlen slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$il_rxlen #define slot$il_txlen slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$il_txlen #define slot$b_rxbuffer slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$b_rxbuffer #define slot$b_txbuffer slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$b_txbuffer #define slot$iq_cpu_sw_comp slot$r_cpu_sw_comp_overlay.slot$iq_cpu_sw_comp #define slot$il_cpu_sw_comp_l slot$r_cpu_sw_comp_overlay.slot$r_cpu_sw_comp_fields.slot$il_cpu_sw_comp_l #define slot$il_cpu_sw_comp_h slot$r_cpu_sw_comp_overlay.slot$r_cpu_sw_comp_fields.slot$il_cpu_sw_comp_h #define slot$iq_console_data_pa slot$r_console_data_pa_overlay.slot$iq_console_data_pa #define slot$il_console_data_pa_l slot$r_console_data_pa_overlay.slot$r_console_data_pa_fields.slot$il_console_data_pa_l #define slot$il_console_data_pa_h slot$r_console_data_pa_overlay.slot$r_console_data_pa_fields.slot$il_console_data_pa_h #define slot$iq_console_data_size slot$r_console_data_size_overlay.slot$iq_console_data_size #define slot$il_console_data_size_l slot$r_console_data_size_overlay.slot$r_console_data_size_fields.slot$il_console_data_size_l #define slot$il_console_data_size_h slot$r_console_data_size_overlay.slot$r_console_data_size_fields.slot$il_console_data_size_h #define slot$iq_cpu_cache slot$r_cpu_cache_overlay.slot$iq_cpu_cache #define slot$il_cpu_cache_l slot$r_cpu_cache_overlay.slot$r_cpu_cache_fields.slot$r_cpu_cache_fields_overlay.slot$il_cpu_cache_l #define slot$il_cpu_cache_h slot$r_cpu_cache_overlay.slot$r_cpu_cache_fields.slot$il_cpu_cache_h #define slot$iq_cycle_count_freq slot$r_cycle_count_freq_overlay.slot$iq_cycle_count_freq #define slot$il_cycle_count_freq_l slot$r_cycle_count_freq_overlay.slot$r_cycle_count_freq_fields.slot$il_cycle_count_freq_l #define slot$il_cycle_count_freq_h slot$r_cycle_count_freq_overlay.slot$r_cycle_count_freq_fields.slot$il_cycle_count_freq_h #define slot$iq_clock_int_freq slot$r_clock_int_freq_overlay.slot$iq_clock_int_freq #define slot$il_clock_int_freq_l slot$r_clock_int_freq_overlay.slot$r_clock_int_freq_fields.slot$il_clock_int_freq_l #define slot$il_clock_int_freq_h slot$r_clock_int_freq_overlay.slot$r_clock_int_freq_fields.slot$il_clock_int_freq_h #define slot$q_mces slot$r_mces_overlay.slot$q_mces #define slot$v_mces_mca slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_mca #define slot$v_mces_cpe slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_cpe #define slot$v_mces_cmc slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_cmc #define slot$v_mces_cpe_dis slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_cpe_dis #define slot$v_mces_cmc_dis slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_cmc_dis #define slot$v_mces_init slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_init #define slot$iq_acpi_id slot$r_acpi_id_overlay.slot$iq_acpi_id #define slot$il_acpi_id_l slot$r_acpi_id_overlay.slot$r_acpi_id_fields.slot$il_acpi_id_l #define slot$il_acpi_id_h slot$r_acpi_id_overlay.slot$r_acpi_id_fields.slot$il_acpi_id_h #define slot$pq_acpi_uid slot$r_acpi_uid_overlay.slot$pq_acpi_uid #define slot$ps_acpi_uid_l slot$r_acpi_uid_overlay.slot$ps_acpi_uid_l #define slot$iq_sys_fw_rev slot$r_sys_fw_rev_overlay.slot$iq_sys_fw_rev #define slot$iw_sys_fw_min_rev slot$r_sys_fw_rev_overlay.slot$r_sys_fw_fields.slot$iw_sys_fw_min_rev #define slot$iw_sys_fw_maj_rev slot$r_sys_fw_rev_overlay.slot$r_sys_fw_fields.slot$iw_sys_fw_maj_rev #define slot$iq_bmc_fw_rev slot$r_bmc_fw_rev_overlay.slot$iq_bmc_fw_rev #define slot$iw_bmc_fw_min_rev slot$r_bmc_fw_rev_overlay.slot$r_bmc_fw_fields.slot$iw_bmc_fw_min_rev #define slot$iw_bmc_fw_maj_rev slot$r_bmc_fw_rev_overlay.slot$r_bmc_fw_fields.slot$iw_bmc_fw_maj_rev #define slot$iq_mp_fw_rev slot$r_mp_fw_rev_overlay.slot$iq_mp_fw_rev #define slot$iw_mp_fw_min_rev slot$r_mp_fw_rev_overlay.slot$r_mp_fw_fields.slot$iw_mp_fw_min_rev #define slot$iw_mp_fw_maj_rev slot$r_mp_fw_rev_overlay.slot$r_mp_fw_fields.slot$iw_mp_fw_maj_rev #endif /* #if !defined(__VAXC) */ #define SLOT$C_LENGTH 1152 #define SLOT$K_LENGTH 1152 #define SLOT$S_SLOTDEF 1072 /* Old size name, synonym */ /********************************* */ /* Memory Cluster Descriptor (MCD) */ /********************************* */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _mcd { /**************************************** */ /* Offset from structure base to next MCD */ /* On IA64 base is the ConfigTree PA */ /* On X86 base is the HWRPB PA */ /* -1 if end of list, 0 if not yet valid */ /**************************************** */ #pragma __nomember_alignment __int64 mcd$iq_usage_link; /*************************************** */ /* First PFN in contiguous range of PFNs described by this MCD */ /*************************************** */ unsigned __int64 mcd$iq_start_pfn; /************************************* */ /* Count of PFNs described by this MCD */ /************************************* */ unsigned __int64 mcd$iq_pfn_count; /******************************************** */ /* UEFI attribute flags passed through to VMS */ /******************************************** */ unsigned __int64 mcd$iq_attribute; /**************************** */ /* Memory Usage Field Values: */ /* 0 - INVALID */ /* 1 - CONSOLE */ /* 2 - NVRAM */ /* 3 - SYSTEM */ /* 4 - SHARED */ /* 5 - MEMORYDISK */ /* 6 - RSVD_DMP Transient Type used by BootMgr */ /* 7 - RSVD_BSR Transient Type used by BootMgr */ /* 8 - HWRPB */ /* 9 - 31 Spare */ /***************************** */ unsigned int mcd$il_usage_bits; /************************************** */ /* Reserved for alignment, must be zero */ /************************************** */ unsigned int mcd$il_mbz_1; } MCD; #define MCDTYPE$K_INVALID 0 #define MCDTYPE$K_CONSOLE 1 #define MCDTYPE$K_NVRAM 2 #define MCDTYPE$K_SYSTEM 3 #define MCDTYPE$K_SHARED 4 #define MCDTYPE$K_MEMORY_DISK 5 #define MCDTYPE$K_RSVD_DMP 6 #define MCDTYPE$K_RSVD_BSR 7 #define MCDTYPE$K_HWRPB 8 #define MCDTYPE$K_KERNEL_BASE 9 /********************************************************** */ /* Head of Physical Memory Cluster Descriptor List (MEMDSC) */ /********************************************************** */ #define HWRPB_PMD$C_LENGTH 24 /* Length of HWRPB_PMD$ */ #define HWRPB_PMD$K_LENGTH 24 /* Length of HWRPB_PMD$ */ /****************************** */ #define HWRPB_PMD$S_NULLPMDDEF 80 /* Size of NULL memory descr. */ /**************************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _pmd { /******************************* */ /* Checksum of Memory Descriptor (MEMDSC+8 through MEMDSC_END) */ /******************************* */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_pmd$iq_chksum; __struct { unsigned int hwrpb_pmd$il_chksum_l; unsigned int hwrpb_pmd$il_chksum_h; } hwrpb_pmd$r_chksum_fields; } hwrpb_pmd$r_chksum_overlay; /*************************************** */ /* Optional Implementation-Specific Data */ /*************************************** */ __union { unsigned __int64 hwrpb_pmd$iq_opt_data; __struct { unsigned int hwrpb_pmd$il_opt_data_l; unsigned int hwrpb_pmd$il_opt_data_h; } hwrpb_pmd$r_opt_data_fields; } hwrpb_pmd$r_opt_data_overlay; /*************************** */ /* Number of MCD's in MEMDSC */ /*************************** */ __union { unsigned __int64 hwrpb_pmd$iq_cluster_count; __struct { unsigned int hwrpb_pmd$il_cluster_count_l; unsigned int hwrpb_pmd$il_cluster_count_h; } hwrpb_pmd$r_cluster_count_fields; } hwrpb_pmd$r_cluster_count_overlay; /* Physical Memory Region (PMR) */ /****************************** */ /* For system with PHYSICALLY DIS-CONTIGUOUS memory, PMR points to */ /* an array of Physical Memory Regions (PMR). */ __union { __union { unsigned __int64 hwrpb_pmd$iq_pmr; /* Start of first region */ __struct { unsigned int hwrpb_pmd$il_pmr_l; unsigned int hwrpb_pmd$il_pmr_h; } hwrpb_pmd$r_pmr_fields; } hwrpb_pmd$r_pmr_overlay; /* For system with PHYSICALLY CONTIGUOUS memory, there are only two regions */ /* defined. The first region describes memory in use by the console, and the */ /* second region describes memory for use by the system. */ __union { unsigned __int64 hwrpb_pmd$iq_cn_pfn_start; /* Start PFN of console region */ __struct { unsigned int hwrpb_pmd$il_cn_pfn_start_l; unsigned int hwrpb_pmd$il_cn_pfn_start_h; } hwrpb_pmd$r_cn_pfn_start_fields; } hwrpb_pmd$r_cn_pfn_start_overlay; /* For system with DYNAMIC memory descriptors, there is only one region defined. It is a */ /* NULL cluster descriptor. It describes the listheads of shared and private memory cluster */ /* descriptors. The first field which is normally the PFN_START field, must be set to -1. */ __union { __int64 hwrpb_pmd$iq_null_mbmo; /* Must be minus one */ __struct { int hwrpb_pmd$il_null_mbmo_l; int hwrpb_pmd$il_null_mbmo_h; } hwrpb_pmd$r_null_mbmo_fields; } hwrpb_pmd$r_null_mbmo_overlay; } hwrpb_pmd$r_pmr_region_overlay; __union { /******************************* */ /* Number of PFN's in the region */ /******************************* */ unsigned __int64 hwrpb_pmd$iq_cn_pfn_count; __struct { unsigned int hwrpb_pmd$il_cn_pfn_count_l; unsigned int hwrpb_pmd$il_cn_pfn_count_h; } hwrpb_pmd$r_cn_pfn_count_fields; /*********************************************** */ /* Must be zero field in NULL cluster descriptor */ /*********************************************** */ __int64 hwrpb_pmd$iq_null_mbz; __struct { int hwrpb_pmd$il_null_mbz_l; int hwrpb_pmd$il_null_mbz_h; } hwrpb_pmd$r_null_mbz_fields; } hwrpb_pmd$r_cn_pfn_count_overlay; __union { /************************************* */ /* Number of tested PFNs in the region */ /************************************* */ unsigned __int64 hwrpb_pmd$iq_cn_test_count; __struct { unsigned int hwrpb_pmd$il_cn_test_count_l; unsigned int hwrpb_pmd$il_cn_test_count_h; } hwrpb_pmd$r_cn_test_count_fields; /*********************************************** */ /* Must be zero field in NULL cluster descriptor */ /*********************************************** */ __int64 hwrpb_pmd$iq_null_test_mbz; /* Must be zero */ __struct { int hwrpb_pmd$il_null_test_mbz_l; int hwrpb_pmd$il_null_test_mbz_h; } hwrpb_pmd$r_null_test_mbz_fields; } hwrpb_pmd$r_cn_test_count_overlay; __union { /********************************** */ /* Virtual Address of Memory bitmap */ /********************************** */ unsigned __int64 hwrpb_pmd$iq_cn_bitmap_va; __struct { unsigned int hwrpb_pmd$il_cn_bitmap_va_l; unsigned int hwrpb_pmd$il_cn_bitmap_va_h; } hwrpb_pmd$r_cn_bitmap_va_fields; /******************************************** */ /* Physical offset to listhead of shared MCDs */ /* in NULL cluster descriptor */ /******************************************** */ unsigned __int64 hwrpb_pmd$iq_null_shr_lh; __struct { unsigned int hwrpb_pmd$il_null_shr_lh_l; unsigned int hwrpb_pmd$il_null_shr_lh_h; } hwrpb_pmd$r_null_shr_lh_fields; } hwrpb_pmd$r_cn_bitmap_va_overlay; __union { /**************************** */ /* Physical Address of bitmap */ /**************************** */ unsigned __int64 hwrpb_pmd$iq_cn_bitmap_pa; __struct { unsigned int hwrpb_pmd$il_cn_bitmap_pa_l; unsigned int hwrpb_pmd$il_cn_bitmap_pa_h; } hwrpb_pmd$r_cn_bitmap_pa_fields; /********************************************** */ /* Physical offset to first MCD in private list */ /* in NULL cluster descriptor */ /********************************************** */ unsigned __int64 hwrpb_pmd$iq_null_prv_offset; __struct { unsigned int hwrpb_pmd$il_null_prv_offset_l; unsigned int hwrpb_pmd$il_null_prv_offset_h; } hwrpb_pmd$r_null_prv_fields; } hwrpb_pmd$r_cn_bitmap_pa_overlay; __union { /******************** */ /* Checksum of bitmap */ /******************** */ unsigned __int64 hwrpb_pmd$iq_cn_bitmap_chksum; __struct { unsigned int hwrpb_pmd$il_cn_bitmap_chksum_l; unsigned int hwrpb_pmd$il_cn_bitmap_chksum_h; } hwrpb_pmd$r_cn_bitmap_chksum_field; /*********************************************** */ /* Must be zero field in NULL cluster descriptor */ /*********************************************** */ __int64 hwrpb_pmd$iq_null_chksum_mbz; __struct { int hwrpb_pmd$il_null_chksum_mbz_l; int hwrpb_pmd$il_null_chksum_mbz_h; } hwrpb_pmd$r_null_chksum_mbz_fields; } hwrpb_pmd$r_cn_bitmap_chksum_overl; __union { /********************* */ /* Cluster Usage Flags */ /********************* */ unsigned __int64 hwrpb_pmd$iq_cn_usage; __struct { unsigned int hwrpb_pmd$il_cn_usage_l; unsigned int hwrpb_pmd$il_cn_usage_h; } hwrpb_pmd$r_cn_usage_fields; /*********************************************** */ /* Must be zero field in NULL cluster descriptor */ /*********************************************** */ __int64 hwrpb_pmd$iq_null_usage_mbz; __struct { int hwrpb_pmd$il_null_usage_mbz_l; int hwrpb_pmd$il_null_usage_mbz_h; } hwrpb_pmd$r_null_usage_mbz_fields; } hwrpb_pmd$r_cn_usage_overlay; /* Start PFN of system region */ /**************************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_pfn_start; __struct { unsigned int hwrpb_pmd$il_sy_pfn_start_l; unsigned int hwrpb_pmd$il_sy_pfn_start_h; } hwrpb_pmd$r_sy_pfn_start_fields; } hwrpb_pmd$r_sy_pfn_start_overlay; /************************** */ /* Number of PFNs in region */ /************************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_pfn_count; __struct { unsigned int hwrpb_pmd$il_sy_pfn_count_l; unsigned int hwrpb_pmd$il_sy_pfn_count_h; } hwrpb_pmd$r_sy_pfn_count_fields; } hwrpb_pmd$r_sy_pfn_count_overlay; /********************************* */ /* Number of tested PFNs in region */ /********************************* */ __union { unsigned __int64 hwrpb_pmd$iq_sy_test_count; __struct { unsigned int hwrpb_pmd$il_sy_test_count_l; unsigned int hwrpb_pmd$il_sy_test_count_h; } hwrpb_pmd$r_sy_test_count_fields; } hwrpb_pmd$r_sy_test_count_overlay; /*************************** */ /* Virtual Address of bitmap */ /*************************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_bitmap_va; __struct { unsigned int hwrpb_pmd$il_sy_bitmap_va_l; unsigned int hwrpb_pmd$il_sy_bitmap_va_h; } hwrpb_pmd$r_sy_bitmap_va_fields; } hwrpb_pmd$r_sy_bitmap_va_overlay; /**************************** */ /* Physical Address of bitmap */ /**************************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_bitmap_pa; __struct { unsigned int hwrpb_pmd$il_sy_bitmap_pa_l; unsigned int hwrpb_pmd$il_sy_bitmap_pa_h; } hwrpb_pmd$r_sy_bitmap_pa_fields; } hwrpb_pmd$r_sy_bitmap_pa_overlay; /******************** */ /* Checksum of bitmap */ /******************** */ __union { unsigned __int64 hwrpb_pmd$iq_sy_bitmap_chksum; __struct { unsigned int hwrpb_pmd$il_sy_bitmap_chksum_l; unsigned int hwrpb_pmd$il_sy_bitmap_chksum_h; } hwrpb_pmd$r_sy_bitmap_chksum_field; } hwrpb_pmd$r_sy_bitmap_chksum_overl; /********************* */ /* Cluster Usage Flags */ /********************* */ __union { unsigned __int64 hwrpb_pmd$iq_sy_usage; __struct { unsigned int hwrpb_pmd$il_sy_usage_l; unsigned int hwrpb_pmd$il_sy_usage_h; } hwrpb_pmd$r_sy_usage_fields; } hwrpb_pmd$r_sy_usage_overlay; } PMD; #if !defined(__VAXC) #define hwrpb_pmd$iq_chksum hwrpb_pmd$r_chksum_overlay.hwrpb_pmd$iq_chksum #define hwrpb_pmd$il_chksum_l hwrpb_pmd$r_chksum_overlay.hwrpb_pmd$r_chksum_fields.hwrpb_pmd$il_chksum_l #define hwrpb_pmd$il_chksum_h hwrpb_pmd$r_chksum_overlay.hwrpb_pmd$r_chksum_fields.hwrpb_pmd$il_chksum_h #define hwrpb_pmd$iq_opt_data hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$iq_opt_data #define hwrpb_pmd$il_opt_data_l hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$r_opt_data_fields.hwrpb_pmd$il_opt_data_l #define hwrpb_pmd$il_opt_data_h hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$r_opt_data_fields.hwrpb_pmd$il_opt_data_h #define hwrpb_pmd$iq_cluster_count hwrpb_pmd$r_cluster_count_overlay.hwrpb_pmd$iq_cluster_count #define hwrpb_pmd$il_cluster_count_l hwrpb_pmd$r_cluster_count_overlay.hwrpb_pmd$r_cluster_count_fields.hwrpb_pmd$il_cluster_count_l #define hwrpb_pmd$il_cluster_count_h hwrpb_pmd$r_cluster_count_overlay.hwrpb_pmd$r_cluster_count_fields.hwrpb_pmd$il_cluster_count_h #define hwrpb_pmd$iq_pmr hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_pmr_overlay.hwrpb_pmd$iq_pmr #define hwrpb_pmd$il_pmr_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_pmr_overlay.hwrpb_pmd$r_pmr_fields.hwrpb_pmd$il_pmr_l #define hwrpb_pmd$il_pmr_h hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_pmr_overlay.hwrpb_pmd$r_pmr_fields.hwrpb_pmd$il_pmr_h #define hwrpb_pmd$iq_cn_pfn_start hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$iq_cn_pfn_start #define hwrpb_pmd$il_cn_pfn_start_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$r_cn_pfn_start_fields\ .hwrpb_pmd$il_cn_pfn_start_l #define hwrpb_pmd$il_cn_pfn_start_h hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$r_cn_pfn_start_fields\ .hwrpb_pmd$il_cn_pfn_start_h #define hwrpb_pmd$iq_null_mbmo hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$iq_null_mbmo #define hwrpb_pmd$il_null_mbmo_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$r_null_mbmo_fields.hwrpb_pm\ d$il_null_mbmo_l #define hwrpb_pmd$il_null_mbmo_h hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$r_null_mbmo_fields.hwrpb_pm\ d$il_null_mbmo_h #define hwrpb_pmd$iq_cn_pfn_count hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$iq_cn_pfn_count #define hwrpb_pmd$il_cn_pfn_count_l hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_cn_pfn_count_fields.hwrpb_pmd$il_cn_pfn_count_l #define hwrpb_pmd$il_cn_pfn_count_h hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_cn_pfn_count_fields.hwrpb_pmd$il_cn_pfn_count_h #define hwrpb_pmd$iq_null_mbz hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$iq_null_mbz #define hwrpb_pmd$il_null_mbz_l hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_null_mbz_fields.hwrpb_pmd$il_null_mbz_l #define hwrpb_pmd$il_null_mbz_h hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_null_mbz_fields.hwrpb_pmd$il_null_mbz_h #define hwrpb_pmd$iq_cn_test_count hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$iq_cn_test_count #define hwrpb_pmd$il_cn_test_count_l hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_cn_test_count_fields.hwrpb_pmd$il_cn_test_count_l #define hwrpb_pmd$il_cn_test_count_h hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_cn_test_count_fields.hwrpb_pmd$il_cn_test_count_h #define hwrpb_pmd$iq_null_test_mbz hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$iq_null_test_mbz #define hwrpb_pmd$il_null_test_mbz_l hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_null_test_mbz_fields.hwrpb_pmd$il_null_test_mbz_l #define hwrpb_pmd$il_null_test_mbz_h hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_null_test_mbz_fields.hwrpb_pmd$il_null_test_mbz_h #define hwrpb_pmd$iq_cn_bitmap_va hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$iq_cn_bitmap_va #define hwrpb_pmd$il_cn_bitmap_va_l hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_cn_bitmap_va_fields.hwrpb_pmd$il_cn_bitmap_va_l #define hwrpb_pmd$il_cn_bitmap_va_h hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_cn_bitmap_va_fields.hwrpb_pmd$il_cn_bitmap_va_h #define hwrpb_pmd$iq_null_shr_lh hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$iq_null_shr_lh #define hwrpb_pmd$il_null_shr_lh_l hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_null_shr_lh_fields.hwrpb_pmd$il_null_shr_lh_l #define hwrpb_pmd$il_null_shr_lh_h hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_null_shr_lh_fields.hwrpb_pmd$il_null_shr_lh_h #define hwrpb_pmd$iq_cn_bitmap_pa hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$iq_cn_bitmap_pa #define hwrpb_pmd$il_cn_bitmap_pa_l hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_cn_bitmap_pa_fields.hwrpb_pmd$il_cn_bitmap_pa_l #define hwrpb_pmd$il_cn_bitmap_pa_h hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_cn_bitmap_pa_fields.hwrpb_pmd$il_cn_bitmap_pa_h #define hwrpb_pmd$iq_null_prv_offset hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$iq_null_prv_offset #define hwrpb_pmd$il_null_prv_offset_l hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_null_prv_fields.hwrpb_pmd$il_null_prv_offset_l #define hwrpb_pmd$il_null_prv_offset_h hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_null_prv_fields.hwrpb_pmd$il_null_prv_offset_h #define hwrpb_pmd$iq_cn_bitmap_chksum hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$iq_cn_bitmap_chksum #define hwrpb_pmd$il_cn_bitmap_chksum_l hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_cn_bitmap_chksum_field.hwrpb_pmd$il_cn_bitma\ p_chksum_l #define hwrpb_pmd$il_cn_bitmap_chksum_h hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_cn_bitmap_chksum_field.hwrpb_pmd$il_cn_bitma\ p_chksum_h #define hwrpb_pmd$iq_null_chksum_mbz hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$iq_null_chksum_mbz #define hwrpb_pmd$il_null_chksum_mbz_l hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_null_chksum_mbz_fields.hwrpb_pmd$il_null_chks\ um_mbz_l #define hwrpb_pmd$il_null_chksum_mbz_h hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_null_chksum_mbz_fields.hwrpb_pmd$il_null_chks\ um_mbz_h #define hwrpb_pmd$iq_cn_usage hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$iq_cn_usage #define hwrpb_pmd$il_cn_usage_l hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_cn_usage_fields.hwrpb_pmd$il_cn_usage_l #define hwrpb_pmd$il_cn_usage_h hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_cn_usage_fields.hwrpb_pmd$il_cn_usage_h #define hwrpb_pmd$iq_null_usage_mbz hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$iq_null_usage_mbz #define hwrpb_pmd$il_null_usage_mbz_l hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_null_usage_mbz_fields.hwrpb_pmd$il_null_usage_mbz_l #define hwrpb_pmd$il_null_usage_mbz_h hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_null_usage_mbz_fields.hwrpb_pmd$il_null_usage_mbz_h #define hwrpb_pmd$iq_sy_pfn_start hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$iq_sy_pfn_start #define hwrpb_pmd$il_sy_pfn_start_l hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$r_sy_pfn_start_fields.hwrpb_pmd$il_sy_pfn_start_l #define hwrpb_pmd$il_sy_pfn_start_h hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$r_sy_pfn_start_fields.hwrpb_pmd$il_sy_pfn_start_h #define hwrpb_pmd$iq_sy_pfn_count hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$iq_sy_pfn_count #define hwrpb_pmd$il_sy_pfn_count_l hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$r_sy_pfn_count_fields.hwrpb_pmd$il_sy_pfn_count_l #define hwrpb_pmd$il_sy_pfn_count_h hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$r_sy_pfn_count_fields.hwrpb_pmd$il_sy_pfn_count_h #define hwrpb_pmd$iq_sy_test_count hwrpb_pmd$r_sy_test_count_overlay.hwrpb_pmd$iq_sy_test_count #define hwrpb_pmd$il_sy_test_count_l hwrpb_pmd$r_sy_test_count_overlay.hwrpb_pmd$r_sy_test_count_fields.hwrpb_pmd$il_sy_test_count_l #define hwrpb_pmd$il_sy_test_count_h hwrpb_pmd$r_sy_test_count_overlay.hwrpb_pmd$r_sy_test_count_fields.hwrpb_pmd$il_sy_test_count_h #define hwrpb_pmd$iq_sy_bitmap_va hwrpb_pmd$r_sy_bitmap_va_overlay.hwrpb_pmd$iq_sy_bitmap_va #define hwrpb_pmd$il_sy_bitmap_va_l hwrpb_pmd$r_sy_bitmap_va_overlay.hwrpb_pmd$r_sy_bitmap_va_fields.hwrpb_pmd$il_sy_bitmap_va_l #define hwrpb_pmd$il_sy_bitmap_va_h hwrpb_pmd$r_sy_bitmap_va_overlay.hwrpb_pmd$r_sy_bitmap_va_fields.hwrpb_pmd$il_sy_bitmap_va_h #define hwrpb_pmd$iq_sy_bitmap_pa hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$iq_sy_bitmap_pa #define hwrpb_pmd$il_sy_bitmap_pa_l hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$r_sy_bitmap_pa_fields.hwrpb_pmd$il_sy_bitmap_pa_l #define hwrpb_pmd$il_sy_bitmap_pa_h hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$r_sy_bitmap_pa_fields.hwrpb_pmd$il_sy_bitmap_pa_h #define hwrpb_pmd$iq_sy_bitmap_chksum hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb_pmd$iq_sy_bitmap_chksum #define hwrpb_pmd$il_sy_bitmap_chksum_l hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb_pmd$r_sy_bitmap_chksum_field.hwrpb_pmd$il_sy_bitma\ p_chksum_l #define hwrpb_pmd$il_sy_bitmap_chksum_h hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb_pmd$r_sy_bitmap_chksum_field.hwrpb_pmd$il_sy_bitma\ p_chksum_h #define hwrpb_pmd$iq_sy_usage hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$iq_sy_usage #define hwrpb_pmd$il_sy_usage_l hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$r_sy_usage_fields.hwrpb_pmd$il_sy_usage_l #define hwrpb_pmd$il_sy_usage_h hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$r_sy_usage_fields.hwrpb_pmd$il_sy_usage_h #endif /* #if !defined(__VAXC) */ #define HWRPB_PMD$S_PMDDEF 136 /* Old size name - synonym */ #define HWRPB_LANG$K_UNKNOWN 0 #define HWRPB_LANG$K_DANISH 48 #define HWRPB_LANG$K_GERMAN 50 #define HWRPB_LANG$K_SWISS 52 #define HWRPB_LANG$K_AMERICAN 54 #define HWRPB_LANG$K_BRITISH 56 #define HWRPB_LANG$K_SPANISH 58 #define HWRPB_LANG$K_FRENCH 60 #define HWRPB_LANG$K_CANADIAN 62 #define HWRPB_LANG$K_ROMANDE 64 #define HWRPB_LANG$K_ITALIAN 66 #define HWRPB_LANG$K_NETHERLANDS 68 #define HWRPB_LANG$K_NORSK 70 #define HWRPB_LANG$K_PORTUGUESE 72 #define HWRPB_LANG$K_SUOMI 74 #define HWRPB_LANG$K_SWEDISH 76 #define HWRPB_LANG$K_VLAAMS 78 /*********************** */ /* Console Routine Block */ /*********************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hwrpb_crb { /************************************* */ /* VA of DISPATCH Procedure Descriptor */ /************************************* */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_crb$iq_va_dispatch_pd; __struct { unsigned int hwrpb_crb$il_va_dispatch_pd_l; unsigned int hwrpb_crb$il_va_dispatch_pd_h; } hwrpb_crb$r_va_dispatch_pd_fields; } hwrpb_crb$r_va_dispatch_pd_overlay; /************************************* */ /* PA of DISPATCH Procedure Descriptor */ /************************************* */ __union { unsigned __int64 hwrpb_crb$iq_pa_dispatch_pd; __struct { unsigned int hwrpb_crb$il_pa_dispatch_pd_l; unsigned int hwrpb_crb$il_pa_dispatch_pd_h; } hwrpb_crb$r_pa_dispatch_pd_fields; } hwrpb_crb$r_pa_dispatch_pd_overlay; /********************************** */ /* VA of FIXUP Procedure Descriptor */ /********************************** */ __union { unsigned __int64 hwrpb_crb$iq_va_fixup_pd; __struct { unsigned int hwrpb_crb$il_va_fixup_pd_l; unsigned int hwrpb_crb$il_va_fixup_pd_h; } hwrpb_crb$r_va_fixup_pd_fields; } hwrpb_crb$r_va_fixup_pd_overlay; /********************************** */ /* PA of FIXUP Procedure Descriptor */ /********************************** */ __union { unsigned __int64 hwrpb_crb$iq_pa_fixup_pd; __struct { unsigned int hwrpb_crb$il_pa_fixup_pd_l; unsigned int hwrpb_crb$il_pa_fixup_pd_h; } hwrpb_crb$r_pa_fixup_pd_fields; } hwrpb_crb$r_pa_fixup_pd_overlay; /******************************** */ /* Number of entries in VA/PA map */ /******************************** */ __union { unsigned __int64 hwrpb_crb$iq_map_count; __struct { unsigned int hwrpb_crb$il_map_count_l; unsigned int hwrpb_crb$il_map_count_h; } hwrpb_crb$r_map_count_fields; } hwrpb_crb$r_map_count_overlay; /****************************** */ /* Number of pages to be mapped */ /****************************** */ __union { unsigned __int64 hwrpb_crb$iq_page_count; __struct { unsigned int hwrpb_crb$il_page_count_l; unsigned int hwrpb_crb$il_page_count_h; } hwrpb_crb$r_page_count_fields; } hwrpb_crb$r_page_count_overlay; /******************* */ /* Console VA/PA map */ /******************* */ __union { unsigned __int64 hwrpb_crb$iq_vapa_map; __struct { unsigned int hwrpb_crb$il_vapa_map_l; unsigned int hwrpb_crb$il_vapa_map_h; } hwrpb_crb$r_vapa_map_fields; } hwrpb_crb$r_vapa_map_overlay; } HWRPB_CRB; #if !defined(__VAXC) #define hwrpb_crb$iq_va_dispatch_pd hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$iq_va_dispatch_pd #define hwrpb_crb$il_va_dispatch_pd_l hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$r_va_dispatch_pd_fields.hwrpb_crb$il_va_dispatch\ _pd_l #define hwrpb_crb$il_va_dispatch_pd_h hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$r_va_dispatch_pd_fields.hwrpb_crb$il_va_dispatch\ _pd_h #define hwrpb_crb$iq_pa_dispatch_pd hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$iq_pa_dispatch_pd #define hwrpb_crb$il_pa_dispatch_pd_l hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$r_pa_dispatch_pd_fields.hwrpb_crb$il_pa_dispatch\ _pd_l #define hwrpb_crb$il_pa_dispatch_pd_h hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$r_pa_dispatch_pd_fields.hwrpb_crb$il_pa_dispatch\ _pd_h #define hwrpb_crb$iq_va_fixup_pd hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$iq_va_fixup_pd #define hwrpb_crb$il_va_fixup_pd_l hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$r_va_fixup_pd_fields.hwrpb_crb$il_va_fixup_pd_l #define hwrpb_crb$il_va_fixup_pd_h hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$r_va_fixup_pd_fields.hwrpb_crb$il_va_fixup_pd_h #define hwrpb_crb$iq_pa_fixup_pd hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$iq_pa_fixup_pd #define hwrpb_crb$il_pa_fixup_pd_l hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$r_pa_fixup_pd_fields.hwrpb_crb$il_pa_fixup_pd_l #define hwrpb_crb$il_pa_fixup_pd_h hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$r_pa_fixup_pd_fields.hwrpb_crb$il_pa_fixup_pd_h #define hwrpb_crb$iq_map_count hwrpb_crb$r_map_count_overlay.hwrpb_crb$iq_map_count #define hwrpb_crb$il_map_count_l hwrpb_crb$r_map_count_overlay.hwrpb_crb$r_map_count_fields.hwrpb_crb$il_map_count_l #define hwrpb_crb$il_map_count_h hwrpb_crb$r_map_count_overlay.hwrpb_crb$r_map_count_fields.hwrpb_crb$il_map_count_h #define hwrpb_crb$iq_page_count hwrpb_crb$r_page_count_overlay.hwrpb_crb$iq_page_count #define hwrpb_crb$il_page_count_l hwrpb_crb$r_page_count_overlay.hwrpb_crb$r_page_count_fields.hwrpb_crb$il_page_count_l #define hwrpb_crb$il_page_count_h hwrpb_crb$r_page_count_overlay.hwrpb_crb$r_page_count_fields.hwrpb_crb$il_page_count_h #define hwrpb_crb$iq_vapa_map hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$iq_vapa_map #define hwrpb_crb$il_vapa_map_l hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$r_vapa_map_fields.hwrpb_crb$il_vapa_map_l #define hwrpb_crb$il_vapa_map_h hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$r_vapa_map_fields.hwrpb_crb$il_vapa_map_h #endif /* #if !defined(__VAXC) */ #define HWRPB_CRB$C_LENGTH 56 /* Length of CRB */ #define HWRPB_CRB$K_LENGTH 56 /* Length of CRB */ #define HWRPB_CRB$S_CRBDEF 56 /* Old size name - synonym */ /****************************** */ /* Virtual/Physical Address Map */ /****************************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _vapamap { /************************* */ /* Console Virtual Address */ /************************* */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_vapamap$iq_va; __struct { unsigned int hwrpb_vapamap$il_va_l; unsigned int hwrpb_vapamap$il_va_h; } hwrpb_vapamap$r_va_fields; } hwrpb_vapamap$r_va_overlay; /************************** */ /* Console Physical Address */ /************************** */ __union { unsigned __int64 hwrpb_vapamap$iq_pa; __struct { unsigned int hwrpb_vapamap$il_pa_l; unsigned int hwrpb_vapamap$il_pa_h; } hwrpb_vapamap$r_pa_fields; } hwrpb_vapamap$r_pa_overlay; /********************* */ /* Page Count of Entry */ /********************* */ __union { unsigned __int64 hwrpb_vapamap$iq_page_count; __struct { unsigned int hwrpb_vapamap$il_page_count_l; unsigned int hwrpb_vapamap$il_page_count_h; } hwrpb_vapamap$r_page_count_fields; } hwrpb_vapamap$r_page_count_overlay; } VAPAMAP; #if !defined(__VAXC) #define hwrpb_vapamap$iq_va hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$iq_va #define hwrpb_vapamap$il_va_l hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$r_va_fields.hwrpb_vapamap$il_va_l #define hwrpb_vapamap$il_va_h hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$r_va_fields.hwrpb_vapamap$il_va_h #define hwrpb_vapamap$iq_pa hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$iq_pa #define hwrpb_vapamap$il_pa_l hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$r_pa_fields.hwrpb_vapamap$il_pa_l #define hwrpb_vapamap$il_pa_h hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$r_pa_fields.hwrpb_vapamap$il_pa_h #define hwrpb_vapamap$iq_page_count hwrpb_vapamap$r_page_count_overlay.hwrpb_vapamap$iq_page_count #define hwrpb_vapamap$il_page_count_l hwrpb_vapamap$r_page_count_overlay.hwrpb_vapamap$r_page_count_fields.hwrpb_vapamap$il_page_co\ unt_l #define hwrpb_vapamap$il_page_count_h hwrpb_vapamap$r_page_count_overlay.hwrpb_vapamap$r_page_count_fields.hwrpb_vapamap$il_page_co\ unt_h #endif /* #if !defined(__VAXC) */ #define HWRPB_VAPAMAP$S_VAPAMAPDEF 24 /* Old size name synonym */ /********************** */ /* Boot Path Descriptor */ /********************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _bootdev { /*********************** */ /* Size of Bootpath Desc */ /*********************** */ #pragma __nomember_alignment __union { unsigned __int64 hwrpb_bootdev$iq_size; __struct { unsigned int hwrpb_bootdev$il_size_l; unsigned int hwrpb_bootdev$il_size_h; } hwrpb_bootdev$r_size_fields; } hwrpb_bootdev$r_size_overlay; /****************************** */ /* Boot Device Path Binary Data */ /****************************** */ __union { unsigned __int64 hwrpb_bootdev$iq_device_path; __struct { unsigned int hwrpb_bootdev$il_device_path_l; unsigned int hwrpb_bootdev$il_device_path_h; } hwrpb_bootdev$r_device_path_fields; } hwrpb_bootdev$r_device_path_overla; } BOOTDEV; #if !defined(__VAXC) #define hwrpb_bootdev$iq_size hwrpb_bootdev$r_size_overlay.hwrpb_bootdev$iq_size #define hwrpb_bootdev$il_size_l hwrpb_bootdev$r_size_overlay.hwrpb_bootdev$r_size_fields.hwrpb_bootdev$il_size_l #define hwrpb_bootdev$il_size_h hwrpb_bootdev$r_size_overlay.hwrpb_bootdev$r_size_fields.hwrpb_bootdev$il_size_h #define hwrpb_bootdev$iq_device_path hwrpb_bootdev$r_device_path_overla.hwrpb_bootdev$iq_device_path #define hwrpb_bootdev$il_device_path_l hwrpb_bootdev$r_device_path_overla.hwrpb_bootdev$r_device_path_fields.hwrpb_bootdev$il_devic\ e_path_l #define hwrpb_bootdev$il_device_path_h hwrpb_bootdev$r_device_path_overla.hwrpb_bootdev$r_device_path_fields.hwrpb_bootdev$il_devic\ e_path_h #endif /* #if !defined(__VAXC) */ #define HWRPB_BOOTDEV$S_BOOTDEVDEF 16 /* Old size name synonym */ /* (GARY - VALIDATE OR ELIMINATE THESE) */ /* Console terminal routines */ #define HWRPB_CRB$K_GETC 1 /* Get a character from console */ #define HWRPB_CRB$K_PUTS 2 /* Put a string to console term */ #define HWRPB_CRB$K_RESET_TERM 3 /* Reset console terminal */ #define HWRPB_CRB$K_SET_TERM_INTR 4 /* Set console terminal int. */ #define HWRPB_CRB$K_SET_TERM_CTL 5 /* Set console terminal controls */ #define HWRPB_CRB$K_PROCESS_KEYCODE 6 /* Process and translate keycode */ #define HWRPB_CRB$K_CONSOLE_OPEN 7 /* Open console for I/O */ #define HWRPB_CRB$K_CONSOLE_CLOSE 8 /* Close console for I/O */ /* (GARY - VALIDATE OR ELIMINATE THESE) */ /* Console Generic IO routines */ #define HWRPB_CRB$K_OPEN 16 /* Open access to I/O device */ #define HWRPB_CRB$K_CLOSE 17 /* Close access to I/O device */ #define HWRPB_CRB$K_IOCTL 18 #define HWRPB_CRB$K_READ 19 /* Perform read operation */ #define HWRPB_CRB$K_WRITE 20 /* Perform write operation */ /* (GARY - VALIDATE OR ELIMINATE THESE) */ /* Console Env. Variable Routines */ #define HWRPB_CRB$K_SET_ENV 32 /* Set an environment varible */ #define HWRPB_CRB$K_RESET_ENV 33 /* Reset an environment variable */ #define HWRPB_CRB$K_GET_ENV 34 /* Fetch an environment varible */ #define HWRPB_CRB$K_SAVE_ENV 35 /* Save an environment varible */ /* (GARY - VALIDATE OR ELIMINATE THESE) */ /* Write/Read FRU EEROM routines */ #define HWRPB_CRB$K_WRITE_EEROM 51 #define HWRPB_CRB$K_READ_EEROM 52 #define HWRPB_CRB$K_NEW_CPU_OWNERSHIP 53 #define HWRPB_CRB$K_RELEASE_TO_FIRMWARE 54 #define HWRPB_CRB$K_GET_HW_ERROR_RECORD 55 /* (GARY - VALIDATE OR ELIMINATE THESE) */ /* Required Environment Variables */ #define HWRPB_CRB$K_AUTO_ACTION 1 #define HWRPB_CRB$K_BOOT_DEV 2 #define HWRPB_CRB$K_BOOTCMD_DEV 3 #define HWRPB_CRB$K_BOOTED_DEV 4 #define HWRPB_CRB$K_BOOT_FILE 5 #define HWRPB_CRB$K_BOOTED_FILE 6 #define HWRPB_CRB$K_BOOT_OSFLAGS 7 #define HWRPB_CRB$K_BOOTED_OSFLAGS 8 #define HWRPB_CRB$K_BOOT_RESET 9 #define HWRPB_CRB$K_DUMP_DEV 10 #define HWRPB_CRB$K_ENABLE_AUDIT 11 #define HWRPB_CRB$K_LICENSE 12 #define HWRPB_CRB$K_CHAR_SET 13 #define HWRPB_CRB$K_LANGUAGE 14 #define HWRPB_CRB$K_TTY_DEV 15 /* (GARY - VALIDATE OR ELIMINATE THESE) */ #define HWRPB_CRB$K_PSWITCH 48 #define HWRPB_CRB$K_SAVE_ERROR_LOG 49 #define HWRPB_CRB$K_HALT_CPU 50 /* (GARY - VALIDATE OR ELIMINATE THESE) */ #define HWRPB_CRB$K_PARTITION 40 #define HWRPB_CRB$K_GALAXY 40 #define HWRPB_CRB$K_BOOT_DUMPKERNEL 41 /************************************************** */ /* Itanium min-state save structure - zero relative */ /* TODO - Create the X86 variant */ /************************************************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _mcamin { #pragma __nomember_alignment unsigned __int64 mcamin$iq_saved_gr_nats; /* NaT bits for saved GRs */ /****************** */ /* Static registers */ /****************** */ unsigned __int64 mcamin$iq_gr1; /* General register 1 */ unsigned __int64 mcamin$iq_gr2; /* General register 2 */ unsigned __int64 mcamin$iq_gr3; /* General register 3 */ unsigned __int64 mcamin$iq_gr4; /* General register 4 */ unsigned __int64 mcamin$iq_gr5; /* General register 5 */ unsigned __int64 mcamin$iq_gr6; /* General register 6 */ unsigned __int64 mcamin$iq_gr7; /* General register 7 */ unsigned __int64 mcamin$iq_gr8; /* General register 8 */ unsigned __int64 mcamin$iq_gr9; /* General register 9 */ unsigned __int64 mcamin$iq_gr10; /* General register 10 */ unsigned __int64 mcamin$iq_gr11; /* General register 11 */ unsigned __int64 mcamin$iq_gr12; /* General register 12 */ unsigned __int64 mcamin$iq_gr13; /* General register 13 */ unsigned __int64 mcamin$iq_gr14; /* General register 14 */ unsigned __int64 mcamin$iq_gr15; /* General register 15 */ /****************** */ /* Bank 0 registers */ /****************** */ unsigned __int64 mcamin$iq_bank0_gr16; /* Bank 0 register 16 */ unsigned __int64 mcamin$iq_bank0_gr17; /* Bank 0 register 17 */ unsigned __int64 mcamin$iq_bank0_gr18; /* Bank 0 register 18 */ unsigned __int64 mcamin$iq_bank0_gr19; /* Bank 0 register 19 */ unsigned __int64 mcamin$iq_bank0_gr20; /* Bank 0 register 20 */ unsigned __int64 mcamin$iq_bank0_gr21; /* Bank 0 register 21 */ unsigned __int64 mcamin$iq_bank0_gr22; /* Bank 0 register 22 */ unsigned __int64 mcamin$iq_bank0_gr23; /* Bank 0 register 23 */ unsigned __int64 mcamin$iq_bank0_gr24; /* Bank 0 register 24 */ unsigned __int64 mcamin$iq_bank0_gr25; /* Bank 0 register 25 */ unsigned __int64 mcamin$iq_bank0_gr26; /* Bank 0 register 26 */ unsigned __int64 mcamin$iq_bank0_gr27; /* Bank 0 register 27 */ unsigned __int64 mcamin$iq_bank0_gr28; /* Bank 0 register 28 */ unsigned __int64 mcamin$iq_bank0_gr29; /* Bank 0 register 29 */ unsigned __int64 mcamin$iq_bank0_gr30; /* Bank 0 register 30 */ unsigned __int64 mcamin$iq_bank0_gr31; /* Bank 0 register 31 */ /****************** */ /* Bank 1 registers */ /****************** */ unsigned __int64 mcamin$iq_bank1_gr16; /* Bank 1 register 16 */ unsigned __int64 mcamin$iq_bank1_gr17; /* Bank 1 register 17 */ unsigned __int64 mcamin$iq_bank1_gr18; /* Bank 1 register 18 */ unsigned __int64 mcamin$iq_bank1_gr19; /* Bank 1 register 19 */ unsigned __int64 mcamin$iq_bank1_gr20; /* Bank 1 register 20 */ unsigned __int64 mcamin$iq_bank1_gr21; /* Bank 1 register 21 */ unsigned __int64 mcamin$iq_bank1_gr22; /* Bank 1 register 22 */ unsigned __int64 mcamin$iq_bank1_gr23; /* Bank 1 register 23 */ unsigned __int64 mcamin$iq_bank1_gr24; /* Bank 1 register 24 */ unsigned __int64 mcamin$iq_bank1_gr25; /* Bank 1 register 25 */ unsigned __int64 mcamin$iq_bank1_gr26; /* Bank 1 register 26 */ unsigned __int64 mcamin$iq_bank1_gr27; /* Bank 1 register 27 */ unsigned __int64 mcamin$iq_bank1_gr28; /* Bank 1 register 28 */ unsigned __int64 mcamin$iq_bank1_gr29; /* Bank 1 register 29 */ unsigned __int64 mcamin$iq_bank1_gr30; /* Bank 1 register 30 */ unsigned __int64 mcamin$iq_bank1_gr31; /* Bank 1 register 31 */ /*************************** */ /* Saved predicate registers */ /*************************** */ unsigned __int64 mcamin$iq_saved_prs; /* Predicate registers */ /***************** */ /* State registers */ /***************** */ unsigned __int64 mcamin$iq_br0; /* BR0 */ unsigned __int64 mcamin$iq_rsc; /* RSC */ unsigned __int64 mcamin$iq_iip; /* IIP */ unsigned __int64 mcamin$iq_ipsr; /* IPSR */ unsigned __int64 mcamin$iq_ifs; /* IFS */ /****************************** */ /* Possibly undefined registers */ /****************************** */ unsigned __int64 mcamin$iq_xip; /* XIP or undefined */ unsigned __int64 mcamin$iq_xpsr; /* XPSR or undefined */ unsigned __int64 mcamin$iq_xfs; /* XFS or undefined */ } MCAMIN; /* MCA Constants: */ #define MCAMIN$K_LENGTH 456 /* Full length of MCAMIN$ */ /********************************************* */ /* Itanium machine check interrupt state block */ /* TODO - Create the X86 variant */ /********************************************* */ #define MCAINT$M_HALTED_IN_CONSOLE 0x1 #define MCAINT$M_CONTEXT_VALID 0x2 #define MCAINT$M_NO_DATA 0x4 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _mcaint { #pragma __nomember_alignment __union { unsigned __int64 mcaint$iq_flags; /* Flags bitmask */ __struct { unsigned mcaint$v_halted_in_console : 1; /* CPU is not running OS software */ unsigned mcaint$v_context_valid : 1; /* Valid data has been dumped into buffer */ unsigned mcaint$v_no_data : 1; /* Hardware returned no information in buffer */ unsigned mcaint$v_fill_1_ : 5; } mcaint$r_flags_fields_overlay; } mcaint$r_flags_overlay; unsigned __int64 mcaint$iq_cpu_id; /* Zero-relative CPU ID of interrupted processor */ unsigned __int64 mcaint$iq_int_type; /* Interrupt type code */ unsigned __int64 mcaint$iq_handler_gp; /* Physical GP of current handler */ unsigned __int64 mcaint$iq_handler_ret; /* Physical PC of handler procedure return */ unsigned __int64 mcaint$iq_handler_ksp; /* Physical KSP of console handler */ unsigned __int64 mcaint$iq_handler_bsp; /* Physical BSP of console handler */ unsigned __int64 mcaint$iq_minstate_save_area; /* Physical address of interrupt min-state save area */ unsigned __int64 mcaint$iq_saved_context; /* Physical address of saved hardware state block */ unsigned __int64 mcaint$iq_processor_state_param; /* Itanium processor state parameter value */ unsigned __int64 mcaint$iq_state_info; /* Interrupt-specific state */ unsigned __int64 mcaint$iq_pal_proc_entry; /* Physical PC of PAL routine entry */ unsigned __int64 mcaint$iq_sal_proc_entry; /* Physical PC of SAL routine entry */ unsigned __int64 mcaint$iq_sal_gp; /* Physical GP of SAL routines */ unsigned __int64 mcaint$iq_sal_return; /* Physical PC of SAL return procedure */ unsigned __int64 mcaint$iq_handler_rnat; /* RNAT of console handler register stack */ unsigned __int64 mcaint$iq_handler_xfr_bsp; /* Physical BSP of console handler */ unsigned __int64 mcaint$iq_handler_rsvd1; /* Reserved cell */ unsigned __int64 mcaint$iq_handler_rsvd2; /* Reserved cell */ unsigned __int64 mcaint$iq_handler_rsvd3; /* Reserved cell */ } MCAINT; #if !defined(__VAXC) #define mcaint$iq_flags mcaint$r_flags_overlay.mcaint$iq_flags #define mcaint$v_halted_in_console mcaint$r_flags_overlay.mcaint$r_flags_fields_overlay.mcaint$v_halted_in_console #define mcaint$v_context_valid mcaint$r_flags_overlay.mcaint$r_flags_fields_overlay.mcaint$v_context_valid #define mcaint$v_no_data mcaint$r_flags_overlay.mcaint$r_flags_fields_overlay.mcaint$v_no_data #endif /* #if !defined(__VAXC) */ /* MCAINT Constants: */ #define MCAINT$K_LENGTH 160 /* Full length of MCAINT$ */ /************************************************************************** */ /* Itanium machine check saved context structure not in minstate save array */ /* TODO - Create the X86 variant */ /************************************************************************** */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _mcasav { #pragma __nomember_alignment unsigned __int64 mcasav$iq_bsp; /* Interrupted BSP pointer */ unsigned __int64 mcasav$iq_bspstore; /* Interrupted BSPSTORE pointer */ unsigned __int64 mcasav$iq_rnat; /* Interrupted RNAT value */ unsigned __int64 mcasav$iq_unat; /* Interrupted UNAT value */ unsigned __int64 mcasav$iq_pfs; /* Interrupted PFS value */ unsigned __int64 mcasav$iq_fpsr; /* Interrupted FPSR value */ unsigned __int64 mcasav$iq_isr; /* Interrupted ISR value */ unsigned __int64 mcasav$iq_ifa; /* Interrupted IFA value */ unsigned __int64 mcasav$iq_itir; /* Interrupted ITIR value */ unsigned __int64 mcasav$iq_iipa; /* Interrupted IIPA value */ unsigned __int64 mcasav$iq_iim; /* Interrupted IIM value */ unsigned __int64 mcasav$iq_iha; /* Interrupted IHA value */ unsigned __int64 mcasav$iq_ccv; /* Interrupted CCV value */ unsigned __int64 mcasav$iq_dcr; /* Interrupted DCR value */ unsigned __int64 mcasav$iq_lc; /* Interrupted LC value */ unsigned __int64 mcasav$iq_ec; /* Interrupted EC value */ unsigned __int64 mcasav$iq_br1; /* Interrupted BR1 value */ unsigned __int64 mcasav$iq_br2; /* Interrupted BR2 value */ unsigned __int64 mcasav$iq_br3; /* Interrupted BR3 value */ unsigned __int64 mcasav$iq_br4; /* Interrupted BR4 value */ unsigned __int64 mcasav$iq_br5; /* Interrupted BR5 value */ unsigned __int64 mcasav$iq_br6; /* Interrupted BR6 value */ unsigned __int64 mcasav$iq_br7; /* Interrupted BR7 value */ char mcasav$t_align1 [8]; /* Assure 32 byte alignment */ unsigned __int64 mcasav$q_f2 [2]; /* F2 */ unsigned __int64 mcasav$q_f3 [2]; /* F3 */ unsigned __int64 mcasav$q_f4 [2]; /* F4 */ unsigned __int64 mcasav$q_f5 [2]; /* F5 */ unsigned __int64 mcasav$q_f6 [2]; /* F6 */ unsigned __int64 mcasav$q_f7 [2]; /* F7 */ unsigned __int64 mcasav$q_f8 [2]; /* F8 */ unsigned __int64 mcasav$q_f9 [2]; /* F9 */ unsigned __int64 mcasav$q_f10 [2]; /* F10 */ unsigned __int64 mcasav$q_f11 [2]; /* F11 */ unsigned __int64 mcasav$q_f12 [2]; /* F12 */ unsigned __int64 mcasav$q_f13 [2]; /* F13 */ unsigned __int64 mcasav$q_f14 [2]; /* F14 */ unsigned __int64 mcasav$q_f15 [2]; /* F15 */ unsigned __int64 mcasav$q_f16 [2]; /* F16 */ unsigned __int64 mcasav$q_f17 [2]; /* F17 */ unsigned __int64 mcasav$q_f18 [2]; /* F18 */ unsigned __int64 mcasav$q_f19 [2]; /* F19 */ unsigned __int64 mcasav$q_f20 [2]; /* F20 */ unsigned __int64 mcasav$q_f21 [2]; /* F21 */ unsigned __int64 mcasav$q_f22 [2]; /* F22 */ unsigned __int64 mcasav$q_f23 [2]; /* F23 */ unsigned __int64 mcasav$q_f24 [2]; /* F24 */ unsigned __int64 mcasav$q_f25 [2]; /* F25 */ unsigned __int64 mcasav$q_f26 [2]; /* F26 */ unsigned __int64 mcasav$q_f27 [2]; /* F27 */ unsigned __int64 mcasav$q_f28 [2]; /* F28 */ unsigned __int64 mcasav$q_f29 [2]; /* F29 */ unsigned __int64 mcasav$q_f30 [2]; /* F30 */ unsigned __int64 mcasav$q_f31 [2]; /* F31 */ unsigned __int64 mcasav$q_f32 [2]; /* F32 */ unsigned __int64 mcasav$q_f33 [2]; /* F33 */ unsigned __int64 mcasav$q_f34 [2]; /* F34 */ unsigned __int64 mcasav$q_f35 [2]; /* F35 */ unsigned __int64 mcasav$q_f36 [2]; /* F36 */ unsigned __int64 mcasav$q_f37 [2]; /* F37 */ unsigned __int64 mcasav$q_f38 [2]; /* F38 */ unsigned __int64 mcasav$q_f39 [2]; /* F39 */ unsigned __int64 mcasav$q_f40 [2]; /* F40 */ unsigned __int64 mcasav$q_f41 [2]; /* F41 */ unsigned __int64 mcasav$q_f42 [2]; /* F42 */ unsigned __int64 mcasav$q_f43 [2]; /* F43 */ unsigned __int64 mcasav$q_f44 [2]; /* F44 */ unsigned __int64 mcasav$q_f45 [2]; /* F45 */ unsigned __int64 mcasav$q_f46 [2]; /* F46 */ unsigned __int64 mcasav$q_f47 [2]; /* F47 */ unsigned __int64 mcasav$q_f48 [2]; /* F48 */ unsigned __int64 mcasav$q_f49 [2]; /* F49 */ unsigned __int64 mcasav$q_f50 [2]; /* F50 */ unsigned __int64 mcasav$q_f51 [2]; /* F51 */ unsigned __int64 mcasav$q_f52 [2]; /* F52 */ unsigned __int64 mcasav$q_f53 [2]; /* F53 */ unsigned __int64 mcasav$q_f54 [2]; /* F54 */ unsigned __int64 mcasav$q_f55 [2]; /* F55 */ unsigned __int64 mcasav$q_f56 [2]; /* F56 */ unsigned __int64 mcasav$q_f57 [2]; /* F57 */ unsigned __int64 mcasav$q_f58 [2]; /* F58 */ unsigned __int64 mcasav$q_f59 [2]; /* F59 */ unsigned __int64 mcasav$q_f60 [2]; /* F60 */ unsigned __int64 mcasav$q_f61 [2]; /* F61 */ unsigned __int64 mcasav$q_f62 [2]; /* F62 */ unsigned __int64 mcasav$q_f63 [2]; /* F63 */ unsigned __int64 mcasav$q_f64 [2]; /* F64 */ unsigned __int64 mcasav$q_f65 [2]; /* F65 */ unsigned __int64 mcasav$q_f66 [2]; /* F66 */ unsigned __int64 mcasav$q_f67 [2]; /* F67 */ unsigned __int64 mcasav$q_f68 [2]; /* F68 */ unsigned __int64 mcasav$q_f69 [2]; /* F69 */ unsigned __int64 mcasav$q_f70 [2]; /* F70 */ unsigned __int64 mcasav$q_f71 [2]; /* F71 */ unsigned __int64 mcasav$q_f72 [2]; /* F72 */ unsigned __int64 mcasav$q_f73 [2]; /* F73 */ unsigned __int64 mcasav$q_f74 [2]; /* F74 */ unsigned __int64 mcasav$q_f75 [2]; /* F75 */ unsigned __int64 mcasav$q_f76 [2]; /* F76 */ unsigned __int64 mcasav$q_f77 [2]; /* F77 */ unsigned __int64 mcasav$q_f78 [2]; /* F78 */ unsigned __int64 mcasav$q_f79 [2]; /* F79 */ unsigned __int64 mcasav$q_f80 [2]; /* F80 */ unsigned __int64 mcasav$q_f81 [2]; /* F81 */ unsigned __int64 mcasav$q_f82 [2]; /* F82 */ unsigned __int64 mcasav$q_f83 [2]; /* F83 */ unsigned __int64 mcasav$q_f84 [2]; /* F84 */ unsigned __int64 mcasav$q_f85 [2]; /* F85 */ unsigned __int64 mcasav$q_f86 [2]; /* F86 */ unsigned __int64 mcasav$q_f87 [2]; /* F87 */ unsigned __int64 mcasav$q_f88 [2]; /* F88 */ unsigned __int64 mcasav$q_f89 [2]; /* F89 */ unsigned __int64 mcasav$q_f90 [2]; /* F90 */ unsigned __int64 mcasav$q_f91 [2]; /* F91 */ unsigned __int64 mcasav$q_f92 [2]; /* F92 */ unsigned __int64 mcasav$q_f93 [2]; /* F93 */ unsigned __int64 mcasav$q_f94 [2]; /* F94 */ unsigned __int64 mcasav$q_f95 [2]; /* F95 */ unsigned __int64 mcasav$q_f96 [2]; /* F96 */ unsigned __int64 mcasav$q_f97 [2]; /* F97 */ unsigned __int64 mcasav$q_f98 [2]; /* F98 */ unsigned __int64 mcasav$q_f99 [2]; /* F99 */ unsigned __int64 mcasav$q_f100 [2]; /* F100 */ unsigned __int64 mcasav$q_f101 [2]; /* F101 */ unsigned __int64 mcasav$q_f102 [2]; /* F102 */ unsigned __int64 mcasav$q_f103 [2]; /* F103 */ unsigned __int64 mcasav$q_f104 [2]; /* F104 */ unsigned __int64 mcasav$q_f105 [2]; /* F105 */ unsigned __int64 mcasav$q_f106 [2]; /* F106 */ unsigned __int64 mcasav$q_f107 [2]; /* F107 */ unsigned __int64 mcasav$q_f108 [2]; /* F108 */ unsigned __int64 mcasav$q_f109 [2]; /* F109 */ unsigned __int64 mcasav$q_f110 [2]; /* F110 */ unsigned __int64 mcasav$q_f111 [2]; /* F111 */ unsigned __int64 mcasav$q_f112 [2]; /* F112 */ unsigned __int64 mcasav$q_f113 [2]; /* F113 */ unsigned __int64 mcasav$q_f114 [2]; /* F114 */ unsigned __int64 mcasav$q_f115 [2]; /* F115 */ unsigned __int64 mcasav$q_f116 [2]; /* F116 */ unsigned __int64 mcasav$q_f117 [2]; /* F117 */ unsigned __int64 mcasav$q_f118 [2]; /* F118 */ unsigned __int64 mcasav$q_f119 [2]; /* F119 */ unsigned __int64 mcasav$q_f120 [2]; /* F120 */ unsigned __int64 mcasav$q_f121 [2]; /* F121 */ unsigned __int64 mcasav$q_f122 [2]; /* F122 */ unsigned __int64 mcasav$q_f123 [2]; /* F123 */ unsigned __int64 mcasav$q_f124 [2]; /* F124 */ unsigned __int64 mcasav$q_f125 [2]; /* F125 */ unsigned __int64 mcasav$q_f126 [2]; /* F126 */ unsigned __int64 mcasav$q_f127 [2]; /* F127 */ } MCASAV; /* MCASAV Constants: */ #define MCASAV$K_LENGTH 2208 /* Full length of MCASAV$ */ /************************************************* */ /* Itanium machine check interrupt state type code */ /* TODO - Create the X86 variant */ /************************************************* */ /* Hardware interrupt type codes */ #define HWINT$K_PROCESSOR_START 1 /* CPU coming out of console mode */ #define HWINT$K_INIT 2 /* INIT interrupt */ #define HWINT$K_MCA 3 /* Machine Check Abort interrupt */ #define HWINT$K_CMC 4 /* Corrected Machine Check interrupt */ #define HWINT$K_CPE 5 /* Corrected Platform Error interrupt */ #pragma __required_pointer_size __save #pragma __required_pointer_size __long typedef HWRPB * HWRPB_PQ; #pragma __required_pointer_size __short typedef HWRPB * HWRPB_PL; #pragma __required_pointer_size __restore /********** END OF X86_64 SECTION ************************************** */ /*IA64 */ /********** END IA64 SECTION ******************************************** */ /********** ALPHA SECTION *********************************************** */ /*** Alpha *** End Section *** */ /********** END ALPHA SECTION ************************************** */ #ifdef EFI64 #pragma pack(pop,hwrpbdef) #endif #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __HWRPBDEF_LOADED */