/***************************************************************************/ /** **/ /** HPE CONFIDENTIAL. This software is confidential proprietary software **/ /** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/ /** authorized to be used, duplicated OR disclosed to anyone without the **/ /** prior written permission of HPE. **/ /** © 2023 Copyright Hewlett-Packard Enterprise Development, LP **/ /** **/ /** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/ /** proprietary software licensed by VMS Software, Inc., and is not **/ /** authorized to be used, duplicated or disclosed to anyone without **/ /** the prior written permission of VMS Software, Inc. **/ /** © 2023 Copyright VMS Software, Inc. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 9-Nov-2023 12:06:42 by OpenVMS SDL V3.7 */ /* Source: 22-SEP-2020 13:10:01 $1$DGA8345:[LIB_H.SRC]HPETDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $HPETDEF ***/ #ifndef __HPETDEF_LOADED #define __HPETDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* Notation: */ /* RW read/write */ /* RO read only */ /* RW1C write a 1 to clear the bit; writes of 0 have no effect */ /* RW0 field should always be written with a zero */ /* RMW field should always be written with whatever value was */ /* previously read */ /* */ /* This structure defines hardware registers. The individual fields are */ /* intentionally not defined because these registers can only be accessed */ /* with longword or quadword references. To look at individual fields */ /* copy the entire quadword to a local and then examine the contents. */ /* Similarly, write an entire quadword from a memory copy, not individual */ /* fields. The exceptions to this rule are for the comparator values and */ /* the FSB interrupt value and address. Since these fields are entire */ /* quadwords or longwords, they can be directly accessed. */ /* All fields in this structure are read/write. */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hpet_timer { #pragma __nomember_alignment unsigned __int64 hpet_timer$iq_config_and_caps; /* RW */ __union { unsigned __int64 hpet_timer$iq_comparator_value64; /* RW Comparator value for 64-bit timer */ unsigned int hpet_timer$il_comparator_value32; /* RW Comparator value for 32-bit timer */ } hpet_timer$r_comp_union; __union { unsigned __int64 hpet_timer$iq_fsb_interrupt_route; /* RW */ __struct { unsigned int hpet_timer$il_fsb_int_val; /* RW Value included in FSB interrupt message */ unsigned int hpet_timer$il_fsb_int_addr; /* RW Address to which FSB interrupt message is written */ } hpet_timer$r_fsb_ints; } hpet_timer$r_fsb_union; unsigned __int64 hpet_timer$iq_reserved; } HPET_TIMER; #if !defined(__VAXC) #define hpet_timer$iq_comparator_value64 hpet_timer$r_comp_union.hpet_timer$iq_comparator_value64 #define hpet_timer$il_comparator_value32 hpet_timer$r_comp_union.hpet_timer$il_comparator_value32 #define hpet_timer$iq_fsb_interrupt_route hpet_timer$r_fsb_union.hpet_timer$iq_fsb_interrupt_route #define hpet_timer$il_fsb_int_val hpet_timer$r_fsb_union.hpet_timer$r_fsb_ints.hpet_timer$il_fsb_int_val #define hpet_timer$il_fsb_int_addr hpet_timer$r_fsb_union.hpet_timer$r_fsb_ints.hpet_timer$il_fsb_int_addr #endif /* #if !defined(__VAXC) */ /* Fields of the HPET_TIMER CONFIGS_AND_CAPS register. */ /* All fields in this register are read/write. */ #define HTIMCFG$M_RESERVED_1 0x1 #define HTIMCFG$M_INT_TYPE_CNF 0x2 #define HTIMCFG$M_INT_ENB_CNF 0x4 #define HTIMCFG$M_TYPE_CNF 0x8 #define HTIMCFG$M_PER_INT_CAP 0x10 #define HTIMCFG$M_SIZE_CAP 0x20 #define HTIMCFG$M_VAL_SET_CNF 0x40 #define HTIMCFG$M_RESERVED_2 0x80 #define HTIMCFG$M_CNF_32MODE 0x100 #define HTIMCFG$M_INT_ROUTE_CNF 0x3E00 #define HTIMCFG$M_FSB_EN_CNF 0x4000 #define HTIMCFG$M_FSB_INT_DEL_CAP 0x8000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _htim_config { #pragma __nomember_alignment __union { unsigned __int64 htimcfg$iq_cfg_register; __struct { unsigned htimcfg$v_reserved_1 : 1; /* RW0 [0] */ unsigned htimcfg$v_int_type_cnf : 1; /* RW [1] 0 => edge, 1 => level */ unsigned htimcfg$v_int_enb_cnf : 1; /* RW [2] interrupt enable */ unsigned htimcfg$v_type_cnf : 1; /* RW [3] periodic interrupt enable */ unsigned htimcfg$v_per_int_cap : 1; /* RO [4] timer capable of periodic interrupts */ unsigned htimcfg$v_size_cap : 1; /* RO [5] 1 => 64 bits, 0 => 32 bits */ unsigned htimcfg$v_val_set_cnf : 1; /* RW [6] periodic accumulator write enable */ unsigned htimcfg$v_reserved_2 : 1; /* RW0 [7] */ unsigned htimcfg$v_cnf_32mode : 1; /* RW [8] force 32-bit timer behavior */ unsigned htimcfg$v_int_route_cnf : 5; /* RW [9-13] I/O APIC interrupt routing */ unsigned htimcfg$v_fsb_en_cnf : 1; /* RW [14] deliver interrupts to FSB */ unsigned htimcfg$v_fsb_int_del_cap : 1; /* RO [15] timer capable of FSB interrupts */ unsigned short int htimcfg$iw_reserved_3; /* RW0 [16-31] */ unsigned int htimcfg$il_int_route_cap; /* RO [32-63] I/O APIC routes allowed */ } htimcfg$r_cfg; } htimcfg$r_htimcfg_union; } HTIM_CONFIG; #if !defined(__VAXC) #define htimcfg$iq_cfg_register htimcfg$r_htimcfg_union.htimcfg$iq_cfg_register #define htimcfg$v_int_type_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_int_type_cnf #define htimcfg$v_int_enb_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_int_enb_cnf #define htimcfg$v_type_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_type_cnf #define htimcfg$v_per_int_cap htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_per_int_cap #define htimcfg$v_size_cap htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_size_cap #define htimcfg$v_val_set_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_val_set_cnf #define htimcfg$v_cnf_32mode htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_cnf_32mode #define htimcfg$v_int_route_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_int_route_cnf #define htimcfg$v_fsb_en_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_fsb_en_cnf #define htimcfg$v_fsb_int_del_cap htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_fsb_int_del_cap #define htimcfg$iw_reserved_3 htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$iw_reserved_3 #define htimcfg$il_int_route_cap htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$il_int_route_cap #endif /* #if !defined(__VAXC) */ #define HTCFG_INT_TYPE$K_EDGE 0 #define HTCFG_INT_TYPE$K_LEVEL 1 #define HTCFG_INT_ENB$K_DISABLE 0 #define HTCFG_INT_ENB$K_ENABLE 1 #define HTCFG_INT_TYPE$K_ONE_SHOT 0 #define HTCFG_INT_TYPE$K_PERIODIC 1 #define HTCFG_SIZE$K_SIZE_32 0 #define HTCFG_SIZE$K_SIZE_64 1 #define HTCFG_VAL_SET$K_ENABLE 1 /* Bit automatically clears after a write */ #define HTCFG_32MODE$K_MODE_64 0 #define HTCFG_32MODE$K_MODE_32 1 #define HTCFG_FSB_EN$K_IOAPIC 0 #define HTCFG_FSB_EN$K_FSB 1 /* The HPET_TIMER FSB_INTERRUPT_ROUTE register defines the MSI */ /* (Message Signaled Interrupt) address and data to be used if the */ /* timer is configured to use FSB (Front Side Bus) interrupts. The */ /* MSI message format is defined in section 10.11 of Volume 3 of */ /* the Intel 64 and IA-32 Architectures Software Developer's Manual. */ /* The address determines which CPU(s) receive the message, and the */ /* data indicates which IDT vector to use. */ #define HTIMFSB$M_VECTOR 0xFF #define HTIMFSB$M_DELMODE 0x700 #define HTIMFSB$M_RESERVED_1 0x3800 #define HTIMFSB$M_LEVEL 0x4000 #define HTIMFSB$M_TRIGMODE 0x8000 #define HTIMFSB$M_RESERVED_2 0xFFFF0000 #define HTIMFSB$M_RESERVED_3 0x300000000 #define HTIMFSB$M_DESTMODE 0x400000000 #define HTIMFSB$M_REDIRHINT 0x800000000 #define HTIMFSB$M_RESERVED_4 0xFF000000000 #define HTIMFSB$M_DEST_ID 0xFF00000000000 #define HTIMFSB$M_FEE_TAG 0xFFF0000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _htim_fsb { #pragma __nomember_alignment __union { unsigned __int64 htimfsb$iq_fsb_register; __struct { unsigned htimfsb$v_vector : 8; /* RW [0-7] destination IDT vector */ unsigned htimfsb$v_delmode : 3; /* RW [8-10] delivery mode to destination */ unsigned htimfsb$v_reserved_1 : 3; /* RW0 [11-13] */ unsigned htimfsb$v_level : 1; /* RW [14] for level interrupts, 0 => deassert, 1 => assert */ unsigned htimfsb$v_trigmode : 1; /* RW [15] 0 => edge, 1 => level */ unsigned htimfsb$v_reserved_2 : 16; /* RW0 [16-31] */ unsigned htimfsb$v_reserved_3 : 2; /* RW0 [32-33] */ unsigned htimfsb$v_destmode : 1; /* RW [34] 0 => physical, 1 => logical, but see documentation */ unsigned htimfsb$v_redirhint : 1; /* RW [35] see documentation */ unsigned htimfsb$v_reserved_4 : 8; /* RW0 [36-43] */ unsigned htimfsb$v_dest_id : 8; /* RW [44-51] destination xAPIC ID or x2APIC ID */ unsigned htimfsb$v_fee_tag : 12; /* RW [52-63] must contain 0xFEE */ } htimfsb$r_fsb; } htimfsb$r_htimfsb_union; } HTIM_FSB; #if !defined(__VAXC) #define htimfsb$iq_fsb_register htimfsb$r_htimfsb_union.htimfsb$iq_fsb_register #define htimfsb$v_vector htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_vector #define htimfsb$v_delmode htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_delmode #define htimfsb$v_level htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_level #define htimfsb$v_trigmode htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_trigmode #define htimfsb$v_destmode htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_destmode #define htimfsb$v_redirhint htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_redirhint #define htimfsb$v_dest_id htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_dest_id #define htimfsb$v_fee_tag htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_fee_tag #endif /* #if !defined(__VAXC) */ #define FSBMSG_DELMODE$K_FIXED 0 #define FSBMSG_DELMODE$K_LOWPRI 1 #define FSBMSG_DELMODE$K_SMI 2 #define FSBMSG_DELMODE$K_RESV_1 3 #define FSBMSG_DELMODE$K_NMI 4 #define FSBMSG_DELMODE$K_INIT 5 #define FSBMSG_DELMODE$K_RESV_2 6 #define FSBMSG_DELMODE$K_EXTINT 7 #define FSBMSG_DESTMODE$K_PHYSICAL 0 #define FSBMSG_DESTMODE$K_LOGICAL 1 #define FSBMSG_FEE_TAG$K_FEE 4078 #define FSBMSG_LEVEL$K_DEASSERT 0 #define FSBMSG_LEVEL$K_ASSERT 1 #define FSBMSG_HINT$K_NONE 0 #define FSBMSG_HINT$K_HINT 1 #define FSBMSG_TRIGMODE$K_EDGE 0 #define FSBMSG_TRIGMODE$K_LEVEL 1 /* This structure defines hardware registers. The individual fields are */ /* intentionally not defined because these registers can only be accessed */ /* with longword or quadword references. To look at individual fields */ /* copy the entire quadword to a local and then examine the contents. */ /* Similarly, write an entire quadword from a memory copy, not individual */ /* fields. */ #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hpet { #pragma __nomember_alignment unsigned __int64 hpet$iq_capabilities_and_id; /* RO */ unsigned __int64 hpet$iq_reserved_1; /* RO */ unsigned __int64 hpet$iq_configuration; /* See field descriptions */ unsigned __int64 hpet$iq_reserved_2; /* RO */ unsigned __int64 hpet$iq_interrupt_status; /* See field descriptions */ unsigned __int64 hpet$iq_reserved_3 [25]; /* RO */ unsigned __int64 hpet$iq_main_counter; /* RW Timer value, writable only when counter is halted */ unsigned __int64 hpet$iq_reserved_4; /* RO */ HPET_TIMER hpet$t_timer [3]; /* See HPET_TIMER description above */ } HPET; /* Fields of the HPET CAPABILITIES_AND_ID register. */ /* RO indicates read only. */ #define HPETCAP$M_NUM_TIM_CAP 0x1F00 #define HPETCAP$M_COUNT_SIZ_CAP 0x2000 #define HPETCAP$M_RESERVED_14 0x4000 #define HPETCAP$M_LEG_ROUTE_CAP 0x8000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hpet_caps { #pragma __nomember_alignment __union { unsigned __int64 hpetcap$iq_cap_register; __struct { unsigned char hpetcap$b_rev_id; /* RO [0-7] Hardware revision */ unsigned hpetcap$v_num_tim_cap : 5; /* RO [8-12] Number of timers provided */ unsigned hpetcap$v_count_siz_cap : 1; /* RO [13] Main counter size, 1 => 64 bits, 0 => 32 bits */ unsigned hpetcap$v_reserved_14 : 1; /* RO [14] */ unsigned hpetcap$v_leg_route_cap : 1; /* RO [15] If set, HPET supports legacy replacement interrupt route option */ unsigned short int hpetcap$iw_vendor_id; /* RO [16-31] 0x8086 means Intel */ unsigned int hpetcap$il_counter_clk_period; /* RO [32-63] Main counter increment period in femtoseconds (1E-15) */ } hpetcap$r_caps; } hpetcap$r_cap_union; } HPET_CAPS; #if !defined(__VAXC) #define hpetcap$iq_cap_register hpetcap$r_cap_union.hpetcap$iq_cap_register #define hpetcap$b_rev_id hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$b_rev_id #define hpetcap$v_num_tim_cap hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$v_num_tim_cap #define hpetcap$v_count_siz_cap hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$v_count_siz_cap #define hpetcap$v_leg_route_cap hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$v_leg_route_cap #define hpetcap$iw_vendor_id hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$iw_vendor_id #define hpetcap$il_counter_clk_period hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$il_counter_clk_period #endif /* #if !defined(__VAXC) */ #define HCAP_SIZE$K_SIZE_32 0 #define HCAP_SIZE$K_SIZE_64 1 #define HCAP_LEG$K_IOAPIC 0 #define HCAP_LEG$K_LEG_ROUTE 1 /* Fields of the HPET CONFIGURATION register. */ /* Only bit 0, ENABLE_CNF is meaningfully writable. For all other bits, */ /* while technically writable, the value written back should be the same */ /* as the value read. */ #define HPETCFG$M_ENABLE_CNF 0x1 #define HPETCFG$M_LEG_RT_CNF 0x2 #define HPETCFG$M_RESERVED_1 0xFC #define HPETCFG$M_RESERVED_2 0xFF00 #define HPETCFG$M_RESERVED_3 0xFFFF0000 #define HPETCFG$M_RESERVED_4 0xFFFFFFFF00000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hpet_config { #pragma __nomember_alignment __union { unsigned __int64 hpetcfg$iq_cfg_register; __struct { unsigned hpetcfg$v_enable_cnf : 1; /* RW [0] Master interrupt enable bit */ unsigned hpetcfg$v_leg_rt_cnf : 1; /* RMW [1] Supports legacy replacement route */ unsigned hpetcfg$v_reserved_1 : 6; /* RMW [2-7] pad out the byte */ unsigned hpetcfg$v_reserved_2 : 8; /* RMW [8-15] pad out the word */ unsigned hpetcfg$v_reserved_3 : 16; /* RMW [16-31] pad out the longword */ unsigned hpetcfg$v_reserved_4 : 32; /* RMW [32-63] pad out the quadword */ } hpetcfg$r_cfg; } hpetcfg$r_cfg_union; } HPET_CONFIG; #if !defined(__VAXC) #define hpetcfg$iq_cfg_register hpetcfg$r_cfg_union.hpetcfg$iq_cfg_register #define hpetcfg$v_enable_cnf hpetcfg$r_cfg_union.hpetcfg$r_cfg.hpetcfg$v_enable_cnf #define hpetcfg$v_leg_rt_cnf hpetcfg$r_cfg_union.hpetcfg$r_cfg.hpetcfg$v_leg_rt_cnf #endif /* #if !defined(__VAXC) */ #define HCFG_ENB$K_DISABLE 0 #define HCFG_ENB$K_ENABLE 1 /* Fields of the HPET INTERRUPT_STATUS register. */ /* All fields in this structure are read/write with caveats. */ /* The interrupt status bits are cleared by writing a 1 to them. Writing a zero to */ /* them has no effect. */ #define HPETSTS$M_T0_INT_STS 0x1 #define HPETSTS$M_T1_INT_STS 0x2 #define HPETSTS$M_T2_INT_STS 0x4 #define HPETSTS$M_T3_INT_STS 0x8 #define HPETSTS$M_T4_INT_STS 0x10 #define HPETSTS$M_T5_INT_STS 0x20 #define HPETSTS$M_T6_INT_STS 0x40 #define HPETSTS$M_T7_INT_STS 0x80 #define HPETSTS$M_T8_INT_STS 0x100 #define HPETSTS$M_T9_INT_STS 0x200 #define HPETSTS$M_T10_INT_STS 0x400 #define HPETSTS$M_T11_INT_STS 0x800 #define HPETSTS$M_T12_INT_STS 0x1000 #define HPETSTS$M_T13_INT_STS 0x2000 #define HPETSTS$M_T14_INT_STS 0x4000 #define HPETSTS$M_T15_INT_STS 0x8000 #define HPETSTS$M_T16_INT_STS 0x10000 #define HPETSTS$M_T17_INT_STS 0x20000 #define HPETSTS$M_T18_INT_STS 0x40000 #define HPETSTS$M_T19_INT_STS 0x80000 #define HPETSTS$M_T20_INT_STS 0x100000 #define HPETSTS$M_T21_INT_STS 0x200000 #define HPETSTS$M_T22_INT_STS 0x400000 #define HPETSTS$M_T23_INT_STS 0x800000 #define HPETSTS$M_T24_INT_STS 0x1000000 #define HPETSTS$M_T25_INT_STS 0x2000000 #define HPETSTS$M_T26_INT_STS 0x4000000 #define HPETSTS$M_T27_INT_STS 0x8000000 #define HPETSTS$M_T28_INT_STS 0x10000000 #define HPETSTS$M_T29_INT_STS 0x20000000 #define HPETSTS$M_T30_INT_STS 0x40000000 #define HPETSTS$M_T31_INT_STS 0x80000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _hpet_int_status { #pragma __nomember_alignment __union { unsigned __int64 hpetsts$iq_sts_register; __struct { __union { unsigned int hpetsts$il_tn_int_sts; /* Bit N set if interrupt active for timer N */ __struct { unsigned hpetsts$v_t0_int_sts : 1; /* RW1C [0] Set if interrupt active for timer 0 */ unsigned hpetsts$v_t1_int_sts : 1; /* RW1C [1] Set if interrupt active for timer 1 */ unsigned hpetsts$v_t2_int_sts : 1; /* RW1C [2] Set if interrupt active for timer 2 */ unsigned hpetsts$v_t3_int_sts : 1; /* RW1C [3] Set if interrupt active for timer 3 */ unsigned hpetsts$v_t4_int_sts : 1; /* RW1C [4] Set if interrupt active for timer 4 */ unsigned hpetsts$v_t5_int_sts : 1; /* RW1C [5] Set if interrupt active for timer 5 */ unsigned hpetsts$v_t6_int_sts : 1; /* RW1C [6] Set if interrupt active for timer 6 */ unsigned hpetsts$v_t7_int_sts : 1; /* RW1C [7] Set if interrupt active for timer 7 */ unsigned hpetsts$v_t8_int_sts : 1; /* RW1C [8] Set if interrupt active for timer 8 */ unsigned hpetsts$v_t9_int_sts : 1; /* RW1C [9] Set if interrupt active for timer 9 */ unsigned hpetsts$v_t10_int_sts : 1; /* RW1C [10] Set if interrupt active for timer 10 */ unsigned hpetsts$v_t11_int_sts : 1; /* RW1C [11] Set if interrupt active for timer 11 */ unsigned hpetsts$v_t12_int_sts : 1; /* RW1C [12] Set if interrupt active for timer 12 */ unsigned hpetsts$v_t13_int_sts : 1; /* RW1C [13] Set if interrupt active for timer 13 */ unsigned hpetsts$v_t14_int_sts : 1; /* RW1C [14] Set if interrupt active for timer 14 */ unsigned hpetsts$v_t15_int_sts : 1; /* RW1C [15] Set if interrupt active for timer 15 */ unsigned hpetsts$v_t16_int_sts : 1; /* RW1C [16] Set if interrupt active for timer 16 */ unsigned hpetsts$v_t17_int_sts : 1; /* RW1C [17] Set if interrupt active for timer 17 */ unsigned hpetsts$v_t18_int_sts : 1; /* RW1C [18] Set if interrupt active for timer 18 */ unsigned hpetsts$v_t19_int_sts : 1; /* RW1C [19] Set if interrupt active for timer 19 */ unsigned hpetsts$v_t20_int_sts : 1; /* RW1C [20] Set if interrupt active for timer 20 */ unsigned hpetsts$v_t21_int_sts : 1; /* RW1C [21] Set if interrupt active for timer 21 */ unsigned hpetsts$v_t22_int_sts : 1; /* RW1C [22] Set if interrupt active for timer 22 */ unsigned hpetsts$v_t23_int_sts : 1; /* RW1C [23] Set if interrupt active for timer 23 */ unsigned hpetsts$v_t24_int_sts : 1; /* RW1C [24] Set if interrupt active for timer 24 */ unsigned hpetsts$v_t25_int_sts : 1; /* RW1C [25] Set if interrupt active for timer 25 */ unsigned hpetsts$v_t26_int_sts : 1; /* RW1C [26] Set if interrupt active for timer 26 */ unsigned hpetsts$v_t27_int_sts : 1; /* RW1C [27] Set if interrupt active for timer 27 */ unsigned hpetsts$v_t28_int_sts : 1; /* RW1C [28] Set if interrupt active for timer 28 */ unsigned hpetsts$v_t29_int_sts : 1; /* RW1C [29] Set if interrupt active for timer 29 */ unsigned hpetsts$v_t30_int_sts : 1; /* RW1C [30] Set if interrupt active for timer 30 */ unsigned hpetsts$v_t31_int_sts : 1; /* RW1C [31] Set if interrupt active for timer 31 */ } hpetsts$r_int; } hpetsts$r_int_union; unsigned int hpetsts$il_reserved; /* RW0 [32-63] */ } hpetsts$r_sts; } hpetsts$r_sts_union; } HPET_INT_STATUS; #if !defined(__VAXC) #define hpetsts$iq_sts_register hpetsts$r_sts_union.hpetsts$iq_sts_register #define hpetsts$il_tn_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$il_tn_int_sts #define hpetsts$v_t0_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t0_int_sts #define hpetsts$v_t1_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t1_int_sts #define hpetsts$v_t2_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t2_int_sts #define hpetsts$v_t3_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t3_int_sts #define hpetsts$v_t4_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t4_int_sts #define hpetsts$v_t5_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t5_int_sts #define hpetsts$v_t6_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t6_int_sts #define hpetsts$v_t7_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t7_int_sts #define hpetsts$v_t8_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t8_int_sts #define hpetsts$v_t9_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t9_int_sts #define hpetsts$v_t10_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t10_int_sts #define hpetsts$v_t11_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t11_int_sts #define hpetsts$v_t12_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t12_int_sts #define hpetsts$v_t13_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t13_int_sts #define hpetsts$v_t14_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t14_int_sts #define hpetsts$v_t15_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t15_int_sts #define hpetsts$v_t16_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t16_int_sts #define hpetsts$v_t17_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t17_int_sts #define hpetsts$v_t18_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t18_int_sts #define hpetsts$v_t19_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t19_int_sts #define hpetsts$v_t20_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t20_int_sts #define hpetsts$v_t21_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t21_int_sts #define hpetsts$v_t22_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t22_int_sts #define hpetsts$v_t23_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t23_int_sts #define hpetsts$v_t24_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t24_int_sts #define hpetsts$v_t25_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t25_int_sts #define hpetsts$v_t26_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t26_int_sts #define hpetsts$v_t27_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t27_int_sts #define hpetsts$v_t28_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t28_int_sts #define hpetsts$v_t29_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t29_int_sts #define hpetsts$v_t30_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t30_int_sts #define hpetsts$v_t31_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t31_int_sts #endif /* #if !defined(__VAXC) */ #ifdef __INITIAL_POINTER_SIZE #pragma __required_pointer_size __save /* Save current pointer size */ #pragma __required_pointer_size __long /* Pointers are 64-bit */ typedef HPET * HPET_PQ; /* Pointer to an HPET structure */ typedef HPET_TIMER * HPET_TIMER_PQ; /* Pointer to an HPET_TIMER structure */ #pragma __required_pointer_size __restore /* Return to previous pointer size */ #else typedef unsigned __int64 HPET_PQ; typedef unsigned __int64 HPET_TIMER_PQ; #endif /* __INITIAL_POINTER_SIZE */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __HPETDEF_LOADED */