/***************************************************************************/ /** **/ /** HPE CONFIDENTIAL. This software is confidential proprietary software **/ /** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/ /** authorized to be used, duplicated OR disclosed to anyone without the **/ /** prior written permission of HPE. **/ /** © 2023 Copyright Hewlett-Packard Enterprise Development, LP **/ /** **/ /** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/ /** proprietary software licensed by VMS Software, Inc., and is not **/ /** authorized to be used, duplicated or disclosed to anyone without **/ /** the prior written permission of VMS Software, Inc. **/ /** © 2023 Copyright VMS Software, Inc. **/ /** **/ /***************************************************************************/ /********************************************************************************************************************************/ /* Created: 9-Nov-2023 12:06:41 by OpenVMS SDL V3.7 */ /* Source: 19-SEP-2003 11:43:04 $1$DGA8345:[LIB_H.SRC]FPSRDEF.SDL;1 */ /********************************************************************************************************************************/ /*** MODULE $FPSRDEF ***/ #ifndef __FPSRDEF_LOADED #define __FPSRDEF_LOADED 1 #pragma __nostandard /* This file uses non-ANSI-Standard features */ #pragma __member_alignment __save #pragma __nomember_alignment #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __save /* Save the previously-defined required ptr size */ #pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ #endif #ifdef __cplusplus extern "C" { #define __unknown_params ... #define __optional_params ... #else #define __unknown_params #define __optional_params ... #endif #ifndef __struct #if !defined(__VAXC) #define __struct struct #else #define __struct variant_struct #endif #endif #ifndef __union #if !defined(__VAXC) #define __union union #else #define __union variant_union #endif #endif /* */ /* Floating Point Status Field */ /* */ /* This structure defines the contents of the SF0, SF1, SF2, SF3 fields in the FPSR below */ /**************************************** */ #define FPSF$M_FTZ 0x1 #define FPSF$M_WRE 0x2 #define FPSF$M_PC 0xC #define FPSF$M_RC 0x30 #define FPSF$M_TD 0x40 #define FPSF$M_V 0x80 #define FPSF$M_D 0x100 #define FPSF$M_Z 0x200 #define FPSF$M_O 0x400 #define FPSF$M_U 0x800 #define FPSF$M_I 0x1000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _fpsf { /* Control fields */ #pragma __nomember_alignment unsigned fpsf$v_ftz : 1; unsigned fpsf$v_wre : 1; unsigned fpsf$v_pc : 2; unsigned fpsf$v_rc : 2; unsigned fpsf$v_td : 1; /* Flags fields */ unsigned fpsf$v_v : 1; unsigned fpsf$v_d : 1; unsigned fpsf$v_z : 1; unsigned fpsf$v_o : 1; unsigned fpsf$v_u : 1; unsigned fpsf$v_i : 1; unsigned fpsf$v_fill_0__1 : 32; unsigned fpsf$v_fill_0__2 : 19; } FPSF; #define FPSR$M_VD 0x1 #define FPSR$M_DD 0x2 #define FPSR$M_ZD 0x4 #define FPSR$M_OD 0x8 #define FPSR$M_UD 0x10 #define FPSR$M_ID 0x20 #define FPSR$M_TRAPS 0x3F #define FPSR$M_SF0 0x7FFC0 #define FPSR$M_SF1 0xFFF80000 #define FPSR$M_SF2 0x1FFF00000000 #define FPSR$M_SF3 0x3FFE00000000000 #define FPSR$M_TRAPS_0_6 0x3F #define FPSR$M_SF0_FTZ 0x40 #define FPSR$M_SF0_WRE 0x80 #define FPSR$M_SF0_PC 0x300 #define FPSR$M_SF0_RC 0xC00 #define FPSR$M_SF0_TD 0x1000 #define FPSR$M_SF0_V 0x2000 #define FPSR$M_SF0_D 0x4000 #define FPSR$M_SF0_Z 0x8000 #define FPSR$M_SF0_O 0x10000 #define FPSR$M_SF0_U 0x20000 #define FPSR$M_SF0_I 0x40000 #define FPSR$M_SF1_FTZ 0x80000 #define FPSR$M_SF1_WRE 0x100000 #define FPSR$M_SF1_PC 0x600000 #define FPSR$M_SF1_RC 0x1800000 #define FPSR$M_SF1_TD 0x2000000 #define FPSR$M_SF1_V 0x4000000 #define FPSR$M_SF1_D 0x8000000 #define FPSR$M_SF1_Z 0x10000000 #define FPSR$M_SF1_O 0x20000000 #define FPSR$M_SF1_U 0x40000000 #define FPSR$M_SF1_I 0x80000000 #define FPSR$M_SF2_FTZ 0x100000000 #define FPSR$M_SF2_WRE 0x200000000 #define FPSR$M_SF2_PC 0xC00000000 #define FPSR$M_SF2_RC 0x3000000000 #define FPSR$M_SF2_TD 0x4000000000 #define FPSR$M_SF2_V 0x8000000000 #define FPSR$M_SF2_D 0x10000000000 #define FPSR$M_SF2_Z 0x20000000000 #define FPSR$M_SF2_O 0x40000000000 #define FPSR$M_SF2_U 0x80000000000 #define FPSR$M_SF2_I 0x100000000000 #define FPSR$M_SF3_FTZ 0x200000000000 #define FPSR$M_SF3_WRE 0x400000000000 #define FPSR$M_SF3_PC 0x1800000000000 #define FPSR$M_SF3_RC 0x6000000000000 #define FPSR$M_SF3_TD 0x8000000000000 #define FPSR$M_SF3_V 0x10000000000000 #define FPSR$M_SF3_D 0x20000000000000 #define FPSR$M_SF3_Z 0x40000000000000 #define FPSR$M_SF3_O 0x80000000000000 #define FPSR$M_SF3_U 0x100000000000000 #define FPSR$M_SF3_I 0x200000000000000 #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #pragma __nomember_alignment __quadword #else #pragma __nomember_alignment #endif typedef struct _fpsr { /* */ /* Floating Point Control and Status Register */ /**************************************** */ #pragma __nomember_alignment __union { unsigned __int64 fpsr$iq_float_status; __struct { unsigned fpsr$v_vd : 1; unsigned fpsr$v_dd : 1; unsigned fpsr$v_zd : 1; unsigned fpsr$v_od : 1; unsigned fpsr$v_ud : 1; unsigned fpsr$v_id : 1; unsigned fpsr$v_fill_1_ : 2; } fpsr$r_trap; __union { __struct { unsigned fpsr$v_traps : 6; unsigned fpsr$v_sf0 : 13; unsigned fpsr$v_sf1 : 13; unsigned fpsr$v_sf2 : 13; unsigned fpsr$v_sf3 : 13; unsigned fpsr$v_rv2 : 6; /* Reserved field above SF3. (Do not change location or name. Used by SWIS_EXCEPTION) */ } fpsr$r_fpsr_fields; __struct { unsigned fpsr$v_traps_0_6 : 6; unsigned fpsr$v_sf0_ftz : 1; unsigned fpsr$v_sf0_wre : 1; unsigned fpsr$v_sf0_pc : 2; unsigned fpsr$v_sf0_rc : 2; unsigned fpsr$v_sf0_td : 1; unsigned fpsr$v_sf0_v : 1; unsigned fpsr$v_sf0_d : 1; unsigned fpsr$v_sf0_z : 1; unsigned fpsr$v_sf0_o : 1; unsigned fpsr$v_sf0_u : 1; unsigned fpsr$v_sf0_i : 1; unsigned fpsr$v_sf1_ftz : 1; unsigned fpsr$v_sf1_wre : 1; unsigned fpsr$v_sf1_pc : 2; unsigned fpsr$v_sf1_rc : 2; unsigned fpsr$v_sf1_td : 1; unsigned fpsr$v_sf1_v : 1; unsigned fpsr$v_sf1_d : 1; unsigned fpsr$v_sf1_z : 1; unsigned fpsr$v_sf1_o : 1; unsigned fpsr$v_sf1_u : 1; unsigned fpsr$v_sf1_i : 1; unsigned fpsr$v_sf2_ftz : 1; unsigned fpsr$v_sf2_wre : 1; unsigned fpsr$v_sf2_pc : 2; unsigned fpsr$v_sf2_rc : 2; unsigned fpsr$v_sf2_td : 1; unsigned fpsr$v_sf2_v : 1; unsigned fpsr$v_sf2_d : 1; unsigned fpsr$v_sf2_z : 1; unsigned fpsr$v_sf2_o : 1; unsigned fpsr$v_sf2_u : 1; unsigned fpsr$v_sf2_i : 1; unsigned fpsr$v_sf3_ftz : 1; unsigned fpsr$v_sf3_wre : 1; unsigned fpsr$v_sf3_pc : 2; unsigned fpsr$v_sf3_rc : 2; unsigned fpsr$v_sf3_td : 1; unsigned fpsr$v_sf3_v : 1; unsigned fpsr$v_sf3_d : 1; unsigned fpsr$v_sf3_z : 1; unsigned fpsr$v_sf3_o : 1; unsigned fpsr$v_sf3_u : 1; unsigned fpsr$v_sf3_i : 1; unsigned fpsr$v_fill_2_ : 6; } fpsr$r_fpsr_sf_bits; } fpsr$r_fpsf_overlay; } fpsr$r_fpsr_overlay; } FPSR; #if !defined(__VAXC) #define fpsr$iq_float_status fpsr$r_fpsr_overlay.fpsr$iq_float_status #define fpsr$v_vd fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_vd #define fpsr$v_dd fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_dd #define fpsr$v_zd fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_zd #define fpsr$v_od fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_od #define fpsr$v_ud fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_ud #define fpsr$v_id fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_id #define fpsr$v_traps fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_traps #define fpsr$v_sf0 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_sf0 #define fpsr$v_sf1 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_sf1 #define fpsr$v_sf2 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_sf2 #define fpsr$v_sf3 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_sf3 #define fpsr$v_rv2 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_rv2 #define fpsr$v_traps_0_6 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_traps_0_6 #define fpsr$v_sf0_ftz fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_ftz #define fpsr$v_sf0_wre fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_wre #define fpsr$v_sf0_pc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_pc #define fpsr$v_sf0_rc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_rc #define fpsr$v_sf0_td fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_td #define fpsr$v_sf0_v fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_v #define fpsr$v_sf0_d fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_d #define fpsr$v_sf0_z fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_z #define fpsr$v_sf0_o fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_o #define fpsr$v_sf0_u fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_u #define fpsr$v_sf0_i fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_i #define fpsr$v_sf1_ftz fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_ftz #define fpsr$v_sf1_wre fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_wre #define fpsr$v_sf1_pc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_pc #define fpsr$v_sf1_rc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_rc #define fpsr$v_sf1_td fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_td #define fpsr$v_sf1_v fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_v #define fpsr$v_sf1_d fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_d #define fpsr$v_sf1_z fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_z #define fpsr$v_sf1_o fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_o #define fpsr$v_sf1_u fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_u #define fpsr$v_sf1_i fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_i #define fpsr$v_sf2_ftz fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_ftz #define fpsr$v_sf2_wre fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_wre #define fpsr$v_sf2_pc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_pc #define fpsr$v_sf2_rc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_rc #define fpsr$v_sf2_td fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_td #define fpsr$v_sf2_v fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_v #define fpsr$v_sf2_d fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_d #define fpsr$v_sf2_z fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_z #define fpsr$v_sf2_o fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_o #define fpsr$v_sf2_u fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_u #define fpsr$v_sf2_i fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_i #define fpsr$v_sf3_ftz fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_ftz #define fpsr$v_sf3_wre fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_wre #define fpsr$v_sf3_pc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_pc #define fpsr$v_sf3_rc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_rc #define fpsr$v_sf3_td fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_td #define fpsr$v_sf3_v fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_v #define fpsr$v_sf3_d fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_d #define fpsr$v_sf3_z fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_z #define fpsr$v_sf3_o fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_o #define fpsr$v_sf3_u fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_u #define fpsr$v_sf3_i fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_i #endif /* #if !defined(__VAXC) */ #define FPSR$K_INITIAL_VALUE_L 40895295 /* Low half: sf0=0x0c sf1=0x4e,sf2=sf3=4c traps set to 0x3f */ #define FPSR$K_INITIAL_VALUE_H 622668 /* Upper half */ #pragma __member_alignment __restore #ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ #pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */ #endif #ifdef __cplusplus } #endif #pragma __standard #endif /* __FPSRDEF_LOADED */